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m 1998 microchip technology inc. preliminary ds40191a-page 1 pic16cr54c devices included in this data sheet: pic16cr54c high-performance risc cpu: only 33 single word instructions to learn all instructions are single cycle (200 ns) except for program branches which are two-cycle operating speed: dc - 20 mhz clock input dc - 200 ns instruction cycle 12-bit wide instructions 8-bit wide data path seven or eight special function hardware registers two-level deep hardware stack direct, indirect and relative addressing modes for data and instructions peripheral features: 8-bit real time clock/counter (tmr0) with 8-bit programmable prescaler power-on reset (por) device reset timer (drt) watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation programmable code-protection power saving sleep mode selectable oscillator options: - rc: low-cost rc oscillator - xt: standard crystal/resonator - hs: high-speed crystal/resonator - lp: power saving, low-frequency crystal cmos technology: low-power, high-speed cmos rom technology fully static design wide-operating voltage and temperature range: - rom commercial/industrial 3.0v to 5.5v low-power consumption - < 2 ma typical @ 5v, 4 mhz - 15 m a typical @ 3v, 32 khz - < 0.6 m a typical standby current (with wdt disabled) @ 3v, 0 c to 70 c device pins i/o rom ram pic16cr54c 18 12 512 25 pin diagrams pdip and soic pic16cr54c ra1 ra0 osc1/clkin osc2/clkout v dd v dd rb7 rb6 rb5 rb4 ra2 ra3 t0cki mclr v pp v ss v ss rb0 rb1 rb2 rb3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 ssop pic16cr54c ra2 ra3 t0cki mclr v pp v ss rb0 rb1 rb2 rb3 1 2 3 4 5 6 7 8 9 10 18 17 16 15 14 13 12 11 ra1 ra0 osc1/clkin osc2/clkout v dd rb7 rb6 rb5 rb4 rom-based 8-bit cmos microcontroller series
pic16cr54c ds40191a -page 2 preliminary 1998 microchip technology inc. de vice diff erences note 1: if y ou change from this de vice to another de vice , please v er ify oscillator char acter istics in y our application. note 2: in pic16l v58a, mclr filter = y es de vice v olta g e rang e oscillator selection (pr ogram) oscillator pr ocess t ec hnology (micr ons) r om equiv alent mclr filter pic16c52 3.0-6.25 user see note 1 0.9 no pic16c54 2.5-6.25 f actor y see note 1 1.2 pic16cr54a no pic16c54a 2.0-6.25 user see note 1 0.9 no pic16c54b 3.0-5.5 user see note 1 0.7 pic16cr54b or pic16cr54c y es pic16c55 2.5-6.25 f actor y see note 1 1.7 no pic16c55a 3.0-5.5 user see note 1 0.7 y es pic16c56 2.5-6.25 f actor y see note 1 1.7 no pic16c56a 3.0-5.5 user see note 1 0.7 pic16cr56a y es pic16c57 2.5-6.25 f actor y see note 1 1.2 no pic16c57c 3.0-5.5 user see note 1 0.7 pic16cr57c y es pic16cr57c 2.5-5.5 f actor y see note 1 0.7 na y es pic16c58a 2.0-6.25 user see note 1 0.9 pic16cr58a no (2) pic16c58b 3.0-5.5 user see note 1 0.7 pic16cr58b y es pic16cr54a 2.5-6.25 f actor y see note 1 1.2 na y es pic16cr54b 2.5-5.5 f actor y see note 1 0.7 na y es pic16cr54c 3.0-5.5 f actor y see note 1 0.7 na y es pic16cr56a 2.5-5.5 f actor y see note 1 0.7 na y es pic16cr57b 2.5-6.25 f actor y see note 1 0.9 na y es pic16cr58a 2.5-6.25 f actor y see note 1 0.9 na y es pic16cr58b 2.5-5.5 f actor y see note 1 0.7 na y es
1998 microchip technology inc. preliminary ds40191a -page 3 pic16cr54c t ab le of contents 1.0 general description ............................................................................................................................... .............. 5 2.0 pic16c5x device varieties ............................................................................................................................... .. 7 3.0 architectural overview ............................................................................................................................... .......... 9 4.0 memory organization ............................................................................................................................... ......... 13 5.0 i/o ports ............................................................................................................................... ............................. 19 6.0 timer0 m odule and tmr0 register .................................................................................................................. 21 7.0 special features of the cpu ............................................................................................................................. 25 8.0 instruction set summary ............................................................................................................................... .... 37 9.0 development support ............................................................................................................................... ......... 49 10.0 electrical characteristics - pic16cr54c .......................................................................................................... 53 11.0 dc and ac characteristics - pic16cr54c ....................................................................................................... 63 12.0 packaging information ............................................................................................................................... ........ 73 appendix a: compatibility ............................................................................................................................... .............. 77 index ............................................................................................................................... ............................................. 79 on-line support ............................................................................................................................... ............................. 81 reader response ............................................................................................................................... .......................... 82 pic16cr54c product identification system ................................................................................................................. 83
pic16cr54c ds40191a -page 4 preliminary 1998 microchip technology inc. notes:
1998 microchip technology inc. preliminary ds40191a -page 5 pic16cr54c 1.0 general description the pic16c5x from microchip t echnology is a f amily of lo w-cost, high p erf or mance , 8-bit, fully static , epr om / r om -based cmos microcontrollers . it emplo ys a risc a rchitecture with only 33 single w ord/single cycle instr uctions . all instr uctions are sin- gle cycle (200 ns) e xcept f or prog r am br anches which tak e tw o cycles . the pic16c5x deliv ers perf or mance an order of magnitude higher than its competitors in the same pr ice categor y . the 12-bit wide instr uctions are highly symmetr ical resulting in 2 :1 code compression o v er other 8-bit microcontrollers in its class . the easy to use and easy to remember instr uction set reduces de v elopment time signi cantly . the pic16c5x products are equipped with special f ea- tures that reduce system cost and po w er requirements . the p o w er-on reset (por) and de vice reset timer (dr t) eliminate the need f or e xter nal reset circuitr y . there are f our oscillator con gur ations to choose from, including the po w er-sa ving lp (lo w p o w er) oscillator and cost s a ving rc oscillator . p o w er sa ving sleep mode , w a tchdog ti mer and code protection f eatures impro v e s ystem cost, po w er and reliability . the uv e r asab le cerdip pac kaged v ersions are ideal f or code de v elopment, while the cost-eff ectiv e on e t ime p rog r ammab le (o tp) v ersions are suitab le f or production in an y v olume . the customer can tak e full adv antage of microchip s pr ice leadership in o tp microcontroller s while bene ting from the o tp s e xibility . the pic16c5x products are suppor ted b y a full-f eatured macro assemb ler , a softw are sim ulator , an in-circuit em ulator , a ? compiler , fuzzy logic suppor t tools , a lo w-cost de v elopment prog r ammer , and a full f eatured prog r ammer . all the tools are suppor ted on i bm pc and compatib le machines . 1.1 applications the pic16c5x ser ies ts perf ectly in applications r ang- ing from high-speed automotiv e and appliance motor control to lo w-po w er remote tr ansmitters/receiv ers , pointing de vices and telecom processors . the epr om technology mak es customizing a pplication prog r ams (tr ansmitter codes , motor speeds , receiv er frequen- cies , etc.) e xtremely f ast and con v enient. the small f ootpr int pac kages , f or through hole or surf ace mount- ing , mak e this microcontroller ser ies perf ect f or a pplica- tions with space limitations . lo w-cost, lo w-po w er , high perf or mance , ease of use and i/o e xibility mak e the pic16c5x ser ies v er y v ersatile e v en in areas where no microcontroller use has been considered bef ore (e .g. , timer functions , replacement of ?lue logic in larger systems , co p rocessor applications).
pic16cr54c ds40191a -page 6 preliminary 1998 microchip technology inc. t ab le 1-1: pic16c5x f amil y of de vices pic16c52 pic16c54s pic16cr54s pic16c55s pic16c56s clock maximum frequency of operation (mhz) 4 20 20 20 20 memory eprom program memory (x12 words) 384 512 512 1k rom program memory (x12 words) 512 ram data memory (bytes) 25 25 25 24 25 peripherals timer module(s) tmr0 tmr0 tmr0 tmr0 tmr0 features i/o pins 12 12 12 20 12 number of instructions 33 33 33 33 33 packages 18-pin dip, soic 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 28-pin dip, soic; 28-pin ssop 18-pin dip, soic; 20-pin ssop all picmicro f amily de vices ha v e p o w er-on reset, selectab le w atchdog timer (e xcept pic16c52), selectab le code protect and high i/o current capability . pic16cr56s pic16c57s pic16cr57s pic16c58s pic16cr58s clock maximum frequency of operation (mhz) 20 20 20 20 20 memory eprom program memory (x12 words) 2k 2k rom program memory (x12 words) 1k 2k 2k ram data memory (bytes) 25 72 72 73 73 peripherals timer module(s) tmr0 tmr0 tmr0 tmr0 tmr0 features i/o pins 12 20 20 12 12 number of instructions 33 33 33 33 33 packages 18-pin dip, soic; 20-pin ssop 28-pin dip, soic; 28-pin ssop 28-pin dip, soic; 28-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop all picmicro f amily de vices ha v e p o w er-on reset, selectab le w atchdog timer (e xcept pic16c52), selectab le code protect and high i/o current capability .
1998 microchip technology inc. preliminary ds40191a -page 7 pic16cr54c 2.0 pic16c5x de vice v arieties a v ar iety of frequency r anges and pac kaging options are a v ailab le . depending on application and production requirements , the proper de vice option can be selected using the inf or mation in this section. w hen placing orders , please use the pic16cr54c product identi cation system at t he bac k o f this data sheet to specify the correct par t n umber . f or the pic16c5x f amily of de vices , there are f our d e vice types , as indicated in the de vice n umber : 1. c , as in pic16c54. these de vices ha v e epr om prog r am memor y and oper ate o v er the standard v oltage r ange . 2. lc , as in pic16lc54a. these de vices ha v e epr om prog r am memor y and oper ate o v er an e xtended v oltage r ange . 3. l v , as in pic16l v54a. these de vices ha v e epr om prog r am memor y and oper ate o v er a 2.0v to 3.8v r ange . 4. cr , as in pic16cr54a. these de vices ha v e r om prog r am memor y and oper ate o v er the standard v oltage r ange . 5. lcr , as in pic16lcr54 b . these de vices ha v e r om prog r am memor y and oper ate o v er an e xtended v oltage r ange . 2.1 u v erasab le de vices (epr om) the uv er asab le v ersion s , off ered in cerdip pac kage s , are o ptimal f or prototype de v elopment and pilot prog r ams u v er asab le de vices c an be p rog r ammed f or a n y of the f our oscillator con gur ations . microchip's picst ar t and pr o ma te prog r ammers both suppor t prog r amming of the pic16cr54c . third par ty prog r ammers also are a v ailab le; ref er to the third p ar ty guide f or a list of sources . 2.2 one-time-pr ogrammab le (o tp) de vices the a v ailability of o tp de vices is especially useful f or customers e xpecting frequent code changes and updates . the o tp de vices , pac kaged in plastic pac kages , per mit the user to prog r am them once . i n addition to the prog r am memor y , the con gur ation bits m ust be prog r ammed. 2.3 quic k-t urnar ound-pr oduction (qtp) de vices microchip off ers a qtp prog r amming ser vice f or f actor y production orders . this ser vice is made a v ailab le f or users who choose not to prog r am a medium to high quantity of units and whose code patter ns ha v e stabiliz ed. the de vices are identical to the o tp de vices b ut with all epr om locations and con gur ation bit o ptions already prog r ammed b y the f actor y . cer tain code and prototype v er i cation procedures apply bef ore production shipments are a v ailab le . please contact y our microchip t echnology sales of ce f or more details . 2.4 serializ ed quic k-t urnar ound-pr oduction (sqtp ) de vices microchip off ers the unique prog r amming ser vice where a f e w user-de ned locations in each de vice are prog r ammed with diff erent ser ial n umbers . the ser ial n umbers ma y be r andom, pseudo-r andom or sequential. the de vices are identical to the o tp de vices b ut with all epr om locations and con gur ation bit o ptions already prog r ammed b y the f actor y . ser ial prog r amming allo ws each de vice to ha v e a unique n umber which can ser v e as an entr y c ode , pass w ord or id n umber . 2.5 read onl y memor y (r om) de vices microchip off ers mask ed r om v ersions of se v er al of the highest v olume par ts , giving the customer a lo w cost option f or high v olume , mature products . sm
pic16cr54c ds40191a -page 8 preliminary 1998 microchip technology inc. notes:
1998 microchip technology inc. preliminary ds40191a -page 9 pic16cr54c 3.0 ar c hitectural over vie w the high perf or mance of the pic16cr54c can be attr ib uted to a n umber of architectur al f eatures commonly f ound in risc microprocessors . t o begin with, the pic16cr54c uses a har v ard architecture in which prog r am and data are accessed on separ ate b uses . this impro v es bandwidth o v er tr aditional v o n neuman n architecture where prog r am and data are f etched on the same b us . separ ating prog r am and data memor y fur ther allo ws instr uctions to be siz ed diff erently than the 8-bit wide data w ord. instr uction op c odes are 12-bit s wide making it possib le to ha v e all single w ord instr uctions . a 12-bit wide prog r am memor y access b us f etches a 12-bit instr uction in a single cycle . a tw o-stage pipeline o v er laps f etch and e x ecution of instr uctions . consequently , all instr uctions ( 33 ) e x ecute in a single cycle ( 200ns @ 20mhz ) e xcept f or prog r am br anches . the pic16cr54c address 512 x 12 of prog r am memor y . all prog r am memor y is inter nal. the pic16cr54c can directly or indirectly address its register les and data memor y . all special function registers including the prog r am counter are mapped in the data memor y . the pic16cr54c has a highly or thogonal (symmetr ical) instr uction set that mak es it possib le to carr y out an y oper ation on an y register using an y addressing mode . this symmetr ical nature and lac k of ?pecial optimal situations mak e prog r amming with the pic16cr54c simple y et ef cient. in addition, the lear ning cur v e is reduced signi cantly . the pic16cr54c de vice c ontain s an 8-bit alu and w or king register . the alu is a gener al pur pose ar ithmetic unit. it perf or ms ar ithmetic and boolean functions betw een data in the w or king register and an y register le . the alu is 8-bits wide and capab le of addition, subtr action, shift and logical oper ations . unless otherwise mentioned, ar ithmetic oper ations are tw o's complement in nature . in tw o-oper and instr uctions , typically one oper and is the w (w or king) register . the other oper and is either a le register or an immediate constant. in single oper and instr uctions , the oper and is either the w register or a le register . the w register is an 8-bit w or king register used f or alu oper ations . it is not an addressab le register . depending on the instr uction e x ecuted, the alu ma y aff ect the v alues of the carr y (c), digit carr y (dc), and zero (z) bits in the st a tus register . the c and dc bits oper ate a s a borr o w and digit borr o w out bit, respectiv ely , in subtr action. see the subwf and addwf instr uctions f or e xamples . a simpli ed b loc k diag r am is sho wn in figure 3-1 , with the corresponding de vice pins descr ibed in t ab le 3-1 .
pic16cr54c ds40191a -page 10 preliminary 1998 microchip technology inc. figure 3-1: pic16cr54c series bloc k dia gram wdt time out 8 st a ck 1 st a ck 2 r om 512 x 12 instr uction register instr uction decoder w a tchdog timer configura tion w ord oscilla t or/ timing & contr ol general purpose register file (sram) 25 bytes wdt/tmr0 prescaler option reg. ?ption ?leep ?ode pr o tect ?sc select direct address tmr0 fr om w fr om w ?ris 5 ?ris 6 fsr trisa por t a trisb por tb t0cki pin 9-11 9-11 12 12 8 w 4 4 4 d a t a b us 8 8 8 8 alu st a tus fr om w clk out 8 9 6 5 osc1 osc2 mclr literals pc ?isable 2 ra3:ra0 rb7:rb0 direct ram address
1998 microchip technology inc. preliminary ds40191a -page 11 pic16cr54c t ab le 3-1: pinout description - pic16cr54c name dip , soic no. ssop no. i/o/p t ype input le vels description ra0 ra1 ra2 ra3 17 1 8 1 2 19 20 1 2 i/o i/o i/o i/o ttl ttl ttl ttl bi-directional i/o por t rb0 rb1 rb2 rb3 rb4 rb5 rb6 rb7 6 7 8 9 10 11 12 13 7 8 9 10 11 12 13 14 i/o i/o i/o i/o i/o i/o i/o i/o ttl ttl ttl ttl ttl ttl ttl ttl bi-directional i/o por t t0cki 3 3 i st cloc k input to t imer0. must be tied to v ss or v dd , if not in use , to reduce current consumption. mclr/ v pp 4 4 i st master clear (reset) input/v er ify v oltage input. this pin is an activ e lo w reset to the de vice . osc1/clkin 16 18 i st (1) oscillator cr ystal input/e xter nal cloc k source input. osc2/clk out 15 17 o oscillator cr ystal output. connects to cr ystal or resonator in cr ystal oscillator mode . in rc mode , osc2 pin outputs clk out which has 1/4 the frequency of osc1, and denotes the instr uction cycle r ate . v dd 14 15,16 p p ositiv e supply f or logic and i/o pins . v ss 5 5,6 p ground ref erence f or logic and i/o pins . legend: i = input, o = output, i/o = input/output, p = po w er , ?= not used, ttl = ttl input, st = schmitt t r igger input note 1: schmitt t r igger input only when in rc mode .
pic16cr54c ds40191a -page 12 preliminary 1998 microchip technology inc. 3.1 cloc king sc heme/ instruction cyc le the cloc k input ( o sc1/clkin pin) is inter nally divided b y f our to gener ate f our non-o v er lapping quadr ature cloc ks namely q1, q2, q3 and q4. inter nally , the prog r am counter is incremented e v er y q1, and the instr uction is f etched from prog r am memor y and latched into instr uction register in q4. it is decoded and e x ecuted dur ing the f ollo wing q1 through q4. the cloc ks and instr uction e x ecution o w is sho wn in figure 3-2 and example 3-1 . 3.2 instruction flo w/pipelining an i nstr uction cycle c onsists of f our q cycles (q1, q2, q3 and q4). the instr uction f etch and e x ecute are pipelined such that f etch tak es one instr uction cycle while decode and e x ecute tak es another instr uction cycle . ho w e v er , due to the pipelining, each instr uction eff ectiv ely e x ecutes in one cycle . if an instr uction causes the prog r am counter to change (e .g. , goto ) then tw o cycles are required to complete the instr uction ( example 3-1 ). a f etch cycle begins with the prog r am counter (pc) incrementing in q1. in the e x ecution cycle , the f etched instr uction is latched into the i nstr uction register (ir) i n cycle q1. this instr uction is then decoded and e x ecuted dur ing the q2, q3, and q4 cycles . data memor y is read dur ing q2 (oper and read) and wr itten dur ing q4 (destination wr ite). figure 3-2: cloc k/instruction cyc le example 3-1: instruction pipeline flo w q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clk out (rc mode) pc pc+1 pc+2 f etch inst (pc) ex ecute inst (pc-1) f etch inst (pc+1) ex ecute inst (pc) f etch inst (pc+2) ex ecute inst (pc+1) inter nal phase cloc k all instr uctions are single cycle , e xcept f or an y prog r am br anches . these tak e tw o cycles since the f etch instr uction is ushed from the pipeline while the ne w instr uction is being f etched and then e x ecuted. 1. movlw 55h f etch 1 ex ecute 1 2. movwf portb f etch 2 ex ecute 2 3. call sub_1 f etch 3 ex ecute 3 4. bsf porta, bit3 f etch 4 flush f etch sub_1 ex ecute sub_1
1998 microchip technology inc. preliminary ds40191a -page 13 pic16cr54c 4.0 memor y or ganization pic16cr54c memor y is organiz ed into prog r am memor y and data memor y . f or de vices with more than 512 b ytes of prog r am memor y , a paging scheme is used. prog r am memor y pages are accessed using one or tw o st a tus register bits . f or de vices with a data memor y register le of more than 32 registers , a banking scheme is used. data memor y banks are accessed using the file selection register (fsr). 4.1 pr ogram memor y or ganization the pic16cr54c has a 9-bit prog r am counter (pc) capab le of addressing a 512 x 12 prog r am memor y space ( figure 4-1 ). accessing a location abo v e the ph ysically implemented address will cause a wr aparound. the reset v ector f or the pic16cr54c is at 1ffh. a nop at the reset v ector location will cause a restar t at location 000h. figure 4-1: pic16cr54c pr ogram memor y map and stac k 4.2 data memor y or ganization data memor y is composed of registers , or b ytes of ram. theref ore , data memor y f or a de vice is speci ed b y its register le . the register le is divided into tw o functional g roups: special function registers and gener al pur pose registers . the special function registers include the tmr0 register , the prog r am counter (pc), the status register , the i/o registers (por ts), and the file select register (fsr). in addition, special pur pose registers are used to control the i/o por t con gur ation and prescaler options . the gener al pur pose registers are used f or data and control inf or mation under command of the instr uctions . f or the pic16cr54c , the register le is composed of 7 special function registers and 25 gener al pur pose registers ( figure 4-2 ). pc<8 : 0> stac k le v el 1 stac k le v el 2 user memor y space call, retlw 9 000h 1ffh reset v ector 0ffh 100h on-chip prog r am memor y 4.2.1 gener al pur pose register file the register le is accessed either directly or indirectly through the le select register fsr ( section 4.7 ). figure 4-2: pic16cr54c register file map 4.2.2 special function registers the special function registers are registers used b y the cpu and per ipher al functions to control the oper ation of the de vice ( t ab le 4-1 ). the special registers can be classi ed into tw o sets . the special function registers associated with the ?ore functions are descr ibed in this section. those related to the oper ation of the per ipher al f eatures are descr ibed in the section f or each per ipher al f eature . file address 00 h 01 h 02 h 03 h 04 h 05 h 06 h 1f h i ndf ( 1) tmr0 pcl st a tus fsr por t a por tb gener al pur pose register s note 1: not a ph ysical register . see section 4.7 0f h 10 h 07h
pic16cr54c ds40191a -page 14 preliminary 1998 microchip technology inc. t ab le 4-1: special function register summar y ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on p o wer -on reset v alue on mclr and wdt reset n/a tris i/o control registers (trisa, trisb) 1111 1111 1111 1111 n/a option contains control bits to con gure timer0 and timer0/wdt prescaler --11 1111 --11 1111 00h indf uses contents of fsr to address data memor y (not a ph ysical register) xxxx xxxx uuuu uuuu 01h tmr0 8-bit r eal-time cloc k/counter xxxx xxxx uuuu uuuu 02h (1) pcl lo w order 8 bits of pc 1111 1111 1111 1111 03h st a tus p a2 p a1 p a0 t o pd z dc c 0001 1xxx 000 q qu uu 04h fsr indirect data memor y address pointer 1x xx xxxx 1u uu uuuu 05h por t a ra3 ra2 ra1 ra0 ---- xxxx ---- uuuu 06h por tb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu legend: shaded b o x es = unimplemented or un used , = unimplemented, read as '0' (if applicab le) x = unkno wn, u = unchanged, q = see the tab les in section 7.7 f or possib le v alues . note 1: the upper b yte of the pr og r am co unter is not directly accessib le . s ee section 4.5 f or an e xplanation of ho w to access these bits .
1998 microchip technology inc. preliminary ds40191a -page 15 pic16cr54c 4.3 st a tus register this register contains the ar ithmetic status of the alu , the reset status , and the page preselect bits f or prog r am memor ies larger than 512 w ords . the st a tus register can be the destination f or an y instr uction, as with an y other register . if the st a tus register is the destination f or an instr uction that aff ects the z, dc or c bits , then the wr ite to these three bits is disab led. these bits are set or cleared according to the de vice logic. fur ther more , the t o and pd bits are not wr itab le . theref ore , the result of an instr uction with the st a tus register as destination ma y be diff erent than intended. f or e xample , clrf status will clear the upper three bits and set the z bit. this lea v es the st a tus register as 000u u1uu (where u = unchanged). it is recommended, theref ore , that only bcf , bsf and movwf instr uctions be used to alter the st a tus register because these instr uctions do not aff ect the z, dc or c bits from the st a tus register . f or other instr uctions , which do aff ect st a tus bits , see section 8.0 , instr uction set summar y . figure 4-3: st a tus register (ad dress:03 h ) r/w - 0 r/w - 0 r/w - 0 r- 1 r- 1 r/w - x r/w - x r/w - x p a2 p a1 p a0 t o pd z dc c r = readab le bit w = wr itab le bi t - n = v alue at por reset bit7 6 5 4 3 2 1 bit0 bit 7: p a2 : this bit un use d at this time . use of the p a2 bit as a gener al pur pose read/wr ite bit is not recommended, since this ma y aff ect upw ard c ompatibility with future products . bit 6-5: not applicab le bit 4: t o : time-out bit 1 = after po w er-up , clrwdt instr uction, or sleep instr uction 0 = a wdt time-out occurred bit 3: pd : p o w er-do wn bit 1 = after po w er-up or b y the clrwdt instr uction 0 = by e x ecution of the sleep instr uction bit 2: z : zero bit 1 = the result of an ar ithmetic or logic oper ation is z ero 0 = the result of an ar ithmetic or logic oper ation is not z ero bit 1: dc : digit carr y/ borro w bit (f or addwf and subwf i nstr uctions) add wf 1 = a carr y f rom the 4th lo w order bit of the result occurred 0 = a c arr y f rom the 4th lo w order bit of the resul t did not occur subwf 1 = a borro w from the 4th lo w order bit of the result did not occur 0 = a borro w from the 4th lo w order bit of the result occurred bit 0: c : carr y/ borro w bit (f or addwf , subwf and rrf , rlf i nstr uctions ) add wf subwf rrf or rlf 1 = a carr y occurred 1 = a borro w did not occur load bit with lsb or msb , respectiv ely 0 = a carr y did not occur 0 = a borro w occurred
pic16cr54c ds40191a -page 16 preliminary 1998 microchip technology inc. 4.4 o ption register the option register is a 6-bit wide , wr ite -o nly register which contains v ar ious control bits to con gure the t imer0/ wdt prescaler and t imer0 . by e x ecuting the option instr uction, the contents of the w register will be tr ansf erred to the option register . a reset sets the option<5:0> bits . figure 4-4: option register u-0 u-0 w - 1 w - 1 w - 1 w - 1 w - 1 w - 1 t0cs t0se psa ps2 ps1 ps0 w = wr itab le bit u = unimplemented bit - n = v alue at por reset bit7 6 5 4 3 2 1 bit0 bit 7 -6 : unimplemented . bit 5 : t0cs : t imer0 cloc k source select bit 1 = t r ansition on t 0cki pin 0 = inter nal instr uction cycle cloc k (clk out) bit 4: t0se : t imer0 source edge select bit 1 = increment on high-to-lo w tr ansition on t 0cki pin 0 = increment on lo w-to-high tr ansition on t 0cki pin bit 3: psa : prescaler assignment bit 1 = prescaler assigned to the wdt (not implemented on pic16c52) 0 = prescaler assigned to t imer0 bit 2-0: ps2:ps0 : prescaler r ate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit v alue t imer0 rate wdt rate (not implemented on pic16c52)
1998 microchip technology inc. preliminary ds40191a -page 17 pic16cr54c 4.5 pr ogram counter as a prog r am instr uction is e x ecuted, the prog r am counter ( pc) will contain the address of the ne xt prog r am instr uction to be e x ecuted. the pc v alue is increased b y one e v er y instr uction cycle , unless an instr uction changes the pc . f or a goto instr uction, bits 8:0 of the pc are pro vided b y the goto instr uction w ord. the pc latch (pcl) is mapped to pc<7:0> ( figure 4-5 and figure 4-6 ). f or a call instr uction, or an y instr uction where the pcl is the destination, bits 7:0 of the pc again are pro vided b y the instr uction w ord. ho w e v er , pc<8> does not come from the instr uction w ord, b ut is alw a ys cleared (figure 4-10 and figure 4-11)/ instr uctions where the pcl is the destination, or modify pcl instr uctions , include movwf pc, addwf pc , and bsf pc, 5 . . note: because pc<8> is cleared in the call instr uction, or an y modify pcl instr uction, all subroutine calls or computed jumps are limited to the rst 256 locations of an y pro- g r am memor y page (512 w ords long). figure 4-5: loading of pc branc h instructions - pic16cr54c 4.5.1 eff ects of reset the prog r am counter is set upon a reset , which means that the pc addresses the last location in the last page i.e ., the reset v ector . the st a tus register page preselect bits are cleared upon a reset , which means that page 0 is pre-selected. theref ore , upon a reset , a goto instr uction at the reset v ector location will automatically cause the prog r am to jump to page 0 . 4.6 stac k pic16c r54c de vice ha s a 9-bit, tw o-le v el hardw are push/pop stac k ( figure 4-1 ). a call instr uction will push the current v alue of stac k 1 into stac k 2 and then push the current prog r am counter v alue , incremented b y one , into stac k le v el 1. if more than tw o sequential call s are e x ecuted, only the most recent tw o retur n addresses are stored. a retlw instr uction will pop the contents of stac k le v el 1 into the prog r am counter and then cop y stac k le v el 2 contents into le v el 1. if more than tw o sequential retlw s are e x ecuted, the stac k will be f illed with the address pre viously stored in le v el 2. note that the w register will be loaded with the liter al v alue speci ed in the instr uction. this is par ticular ly useful f or the implementation of data look-up tab les within the prog r am memor y . pc 8 7 0 pcl pc 8 7 0 pcl reset to '0' i nstr uction w ord i nstr uction w ord goto instruction call or modify pcl instruction
pic16cr54c ds40191a -page 18 preliminary 1998 microchip technology inc. 4.7 indirect data ad dressing; indf and fsr register s the indf register is not a ph ysical register . addressing indf actually addresses the register whose address is contained in the fsr register ( fsr is a pointer ). this is indirect addressing. example 4-1: indirect ad dressing register le 05 contains the v alue 10h register le 06 contains the v alue 0ah load the v alue 05 into the fsr register a read of the indf register will retur n the v alue of 10h increment the v alue of the fsr register b y one (fsr = 06) a read of the indr register no w will retur n the v alue of 0ah. reading indf itself indirectly (fsr = 0) will produce 00h. wr iting to the indf register indirectly results in a no-oper ation (although st a tus bits ma y be aff ected). a simple prog r am to clear ram locations 10h-1fh using indirect addressing is sho wn in example 4-2 . example 4-2: ho w t o clear ram using indirect ad dressing movlw 0x10 ; initialize pointer movwf fsr ; to ram next clrf indf ; clear indf register incf fsr,f ;inc pointer btfsc fsr,4 ;all done? goto next ;no, clear next continue : ;yes, continue the fsr is a 5-bit ( pic16cr54c) wide register . it is used in conjunction with the indf register to indirectly address the data memor y area. the fsr<4:0> bits are used to select data memor y addresses 00h to 1fh. p ic16c r54c: do not use banking. fsr<6:5> are unimplemented and read as '1's . figure 4-6: direct/indirect ad dressing note 1: f or register map detail see section 4.2 . bank location select location select bank select indirect ad dressing direct ad dressing data memor y (1) 0f h 10 h bank 0 0 4 5 6 (fsr) 00 00 h 1f h (opcode) 0 4 5 6 (fsr)
1998 microchip technology inc. preliminary ds40191a -page 19 pic16cr54c 5.0 i/o p or ts as with an y other register , the i/o registers can be wr itten and read under prog r am control. ho w e v er , read instr uctions (e .g., movf portb,w ) alw a ys read the i/o pins independent of the pin s input/output modes . on reset , all i/o por ts are de ned as input (inputs are at hi-impedance) since the i/o control registers (trisa, trisb , trisc) are all set. 5.1 por t a por t a is a 4-bit i/o register . only the lo w order 4 bits are used (ra3:ra0). bits 7-4 are unimplemented and read as '0's . 5.2 por tb por tb is an 8-bit i/o register (por tb<7:0>). 5.3 tris register s the output dr iv er control registers are loaded with the contents of the w register b y e x ecuting the tris f instr uction. a '1' from a tris register bit puts the corresponding output dr iv er in a hi-impedance mode . a '0' puts the contents of the output data latch on the selected pins , enab ling the output b uff er . the tris registers are ?r ite-only and are set (output dr iv ers disab led) upon reset . 5.4 i/o interfacing the equiv alent circuit f or an i/o por t pin is sho wn in figure 5-1 . all por ts ma y be used f or both input and output oper ation. f or input oper ations these por ts are non-latching. an y input m ust be present until read b y an input instr uction (e .g., movf portb, w ). the note: a read of the por ts reads the pins , not the output data latches . that is , if an output dr iv er on a pin is enab led and dr iv en high, b ut the e xter nal system is holding it lo w , a read of the por t will indicate that the pin is lo w . outputs are latched and remain unchanged until the output latch is re wr itten. t o use a por t pin as output, the corresponding direction control bit (in trisa, trisb) m ust be cleared (= 0). f or use as an input, the corresponding tris bit m ust be set. an y i/o pin can be prog r ammed individually as input or output. figure 5-1: equiv alent cir cuit f or a single i/o pin note 1: i/o pins ha v e protection diodes to v dd and v ss . data bu s q d q ck q d q ck p n wr p or t tris ? data tris rd p or t v ss v dd i/o p in (1) w r eg l atch l atch reset t ab le 5-1: s ummar y of p or t register s ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on p o wer -on reset v alue on mclr and wdt reset n/a tris i/o control registers (trisa, trisb) 1111 1111 1111 1111 05h por t a ra3 ra2 ra1 ra0 ---- xxxx ---- uuuu 06h por tb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu legend: shaded b o x es = unimplemented , read as ?? = unimplemented, read as '0', x = unkno wn, u = unchange d
pic16cr54c ds40191a -page 20 preliminary 1998 microchip technology inc. 5.5 i/o pr ogramming considerations 5.5.1 bi-directional i/o p or ts some instr uctions oper ate inter nally as read f ollo w ed b y wr ite oper ations . the bcf and bsf instr uctions , f or e xample , read the entire por t into the cpu , e x ecute the bit oper ation and re-wr ite the result. caution m ust be used when these instr uctions are applied to a por t where one or more pins are used as input/outputs . f or e xample , a bsf oper ation on bit5 of por tb will cause all eight bits of por tb to be read into the cpu , bit5 to be set and the por tb v alue to be wr itten to the output latches . if another bit of por tb is used as a bi-directional i/o pin (sa y bit0) and it is de ned as an input at this time , the input signal present on the pin itself w ould be read into the cpu and re wr itten to the data latch of this par ticular pin, o v erwr iting the pre vious content. as long as the pin sta ys in the input mode , no prob lem occurs . ho w e v er , if bit0 is s witched into output mode later on, the content of the data latch ma y no w be unkno wn. example 5-1 sho ws the eff ect of tw o sequential read-modify-wr ite instr uctions (e .g., bcf, bsf , etc.) on an i/o por t. a pin activ ely outputting a high or a lo w should not be dr iv en from e xter nal de vices at the same time in order to change the le v el on this pin (?ired-or? ?ired-and?. the resulting high output currents ma y damage the chip . example 5-1: read-modify-write instructions on an i/o p or t ;initial port settings ; portb<7:4> inputs ; portb<3:0> outputs ;portb<7:6> have external pull-ups and are ;not connected to other circuitry ; ; port latch port pins ; ---------- ---------- bcf portb, 7 ;01pp pppp 11pp pppp bcf portb, 6 ;10pp pppp 11pp pppp movlw 03fh ; tris portb ;10pp pppp 10pp pppp ; ;note that the user may have expected the pin ;values to be 00pp pppp. the 2nd bcf caused ;rb7 to be latched as the pin value (high). 5.5.2 successiv e oper ations on i/o p or ts the actual wr ite to an i/o por t happens at the end of an instr uction cycle , whereas f or reading, the data m ust be v alid at the beginning of the instr uction cycle ( figure 5-2 ). theref ore , care m ust be e x ercised if a wr ite f ollo w ed b y a read oper ation is carr ied out on the same i/o por t. the sequence of instr uctions should allo w the pin v oltage to stabiliz e (load dependent) bef ore the ne xt instr uction, which causes that le to be read into the cpu , is e x ecuted. otherwise , the pre vious state of that pin ma y be read into the cpu r ather than the ne w state . when in doubt, it is better to separ ate these instr uctions with a nop or another instr uction not accessing this i/o por t. figure 5-2: successive i/o operation pc pc + 1 pc + 2 pc + 3 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instr uction f etched rb 7:rb0 mo vwf por tb nop p or t pin sampled here nop mo vf por tb ,w instr uction e x ecuted mo vwf por tb (wr ite to por tb ) nop mo vf por tb ,w this e xample sho ws a wr ite to por tb f ollo w ed b y a read from por tb . (read por tb ) p or t pin wr itten h ere
1998 microchip technology inc. preliminary ds40191a -page 21 pic16cr54c 6.0 timer0 m odule and tmr0 register the t imer0 module h as the f ollo wing f eatures: 8-bit timer/counter register , tmr0 - readab le and wr itab le 8-bit softw are prog r ammab le prescaler inter nal or e xter nal cloc k select - edge select f or e xter nal cloc k figure 6-1 is a simpli ed b loc k diag r am of the t imer0 module , while figure 6-2 sho ws the electr ical str ucture of the t imer0 i nput. timer mode is selected b y clear ing the t0 c s b it (option<5>). i n timer mode , the t imer0 module will increment e v er y instr uction cycle (without prescaler). i f tmr0 register is wr itten, the increment is inhibited f or the f ollo wing tw o cycles ( figure 6-3 and figure 6-4 ). t he user can w or k around this b y wr iting an adjusted v alue to the tmr0 register . counter mode is selected b y setting the t0cs b it (option<5>). i n this mode , t imer0 will increment either on e v er y r ising or f alling edge of pin t 0cki. t he incrementing edge is deter mined b y the s ource edge s elect bit t0se (option<4>). c lear ing the t0se bit selects the r ising edge . r estr ictions on the e xter nal cloc k input are d iscussed in detail in section 6.1 . the prescaler ma y be used b y either t he t imer0 module or t he w a tchdog ti mer , b ut not both . t he prescaler assignment is controlled in softw are b y the control bit p sa (option<3>). c lear ing the psa bit will assign the prescaler to t imer0 . t he prescaler is n ot r eadab le o r wr itab le . w hen the prescaler is assigned to the t imer0 module , prescale v alue s of 1:2, 1:4, . .., 1:256 are selectab le . section 6.2 details the oper ation of the prescaler . a summar y of registers associated with the timer0 module is f ound in t ab le 6-1 . figure 6-1: t imer0 bloc k dia gram figure 6-2: electri ca l structure of t0cki pin note 1: b its t 0 cs , t0 se, p sa, ps2, ps1 and ps0 are located in the option register . 2: t he prescaler is shared with the w atchdog timer ( figure 6-6 ). t0cki t0se (1) 0 1 1 0 pin t0cs (1) f osc /4 prog r ammab le prescaler (2) sync with inter nal cl oc ks tmr0 reg psout (2 cycle dela y) psout data b us 8 psa (1) ps2, ps1, ps0 (1) 3 sync v ss v ss r in schmitt t r igger n input buff er t0cki pin note 1: esd protection circuits (1) (1)
pic16cr54c ds40191a -page 22 preliminary 1998 microchip technology inc. figure 6-3: t imer0 timing: i nternal cloc k/no prescale figure 6-4: t imer0 timing: internal cloc k/prescale 1:2 t ab le 6-1: register s associated with timer0 a d dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on p o wer -on reset v alue on mclr and wdt reset 0 1h tmr0 timer0 - 8-bit real-time cloc k/counter xxxx xxxx uuuu uuuu n /a option t0cs t0se psa ps2 ps1 ps0 --11 1111 --11 1111 legend: shaded cells: unimplemented bits , - = unimplemented , x = unkno wn, u = unchanged, pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (prog r am counter) instr uction f etch timer0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 t0+1 t0+2 nt0 nt0 nt0 nt0+1 nt0+2 mo vwf tmr0 mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w wr ite tmr0 e x ecuted read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instr uction ex ecuted pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (prog r am counter) instr uction f etch timer0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 nt0+1 mo vwf tmr0 mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w wr ite tmr0 e x ecuted read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 t0+1 nt0 instr uction ex ecute t 0
1998 microchip technology inc. preliminary ds40191a -page 23 pic16cr54c 6.1 using t imer0 with an external cloc k when an e xter nal cloc k input is used f or t imer0 , it m ust meet cer tain requirements . the e xter nal cloc k requirement is due to i nter nal phase cloc k ( t osc ) synchronization. also , there is a dela y in the actual incrementing of t imer0 after synchronization. 6.1.1 exter nal cloc k synchronization when no prescaler is used, the e xter nal cloc k input is the same as the prescaler output. the sy nchroniz ation of t 0cki with the inter nal phase cloc ks is accomplished b y s ampling the prescaler output on the q2 and q4 cycles of the inter nal phase cloc ks ( figure 6-5 ). t heref ore , it is necessar y f or t0cki to be high f or at least 2 t osc ( and a small rc dela y of 20 ns ) and lo w f or at least 2 t osc ( and a small rc dela y of 20 ns) . r ef er to the e lectr ical speci cation of the desired de vice . when a prescaler is used, the e xter nal cloc k input is divided b y the asynchronous r ipple c ounter -t ype prescaler so t hat the prescaler output is symmetr ical. f or the e xter nal cloc k to meet the sampling requirement, the r ipple counter m ust be tak en into account. theref ore , it is necessar y f or t0cki to ha v e a per iod of at least 4 t osc ( and a small rc dela y of 40 ns ) divided b y the prescaler v alue . t he only requirement o n t0cki high and lo w time is that the y do not violate t he minim um pulse width requirement of 10 ns . r ef er to p ar ameters 40, 41 and 42 in the e lectr ical speci cation of the desired de vice . 6.1.2 t imer0 increment dela y since the prescaler output is synchroniz ed with the inter nal cloc ks , there is a small dela y from the time the e xter nal cloc k edge occurs to the time the t imer0 module is actually incremented. figure 6-5 sho ws the dela y from the e xter nal cloc k edge to the timer incrementing . figure 6-5: timer0 timing with external cloc k increment timer0 (q4) external clock input or q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 t imer0 t0 t0 + 1 t0 + 2 small pulse misses sampling external clock/prescaler output after sampling (3) note 1: 2 : 3 : delay from clock input change to t imer0 increment is 3 tosc t o 7 tosc. (duration of q = tosc) . therefore, the error in measuring the interval between two edges on t imer0 input = 4 tosc m ax. external clock if no prescaler selected, prescaler output otherwise. the arrows indicate the points in time where sampling occurs. prescaler output (2) (1)
pic16cr54c ds40191a -page 24 preliminary 1998 microchip technology inc. 6.2 prescaler an 8-bit counter is a v ailab le as a prescaler f or the timer0 module , or as a postscaler f or the w atchdog timer (wdt) (wdt postscaler not implemented on pic16c52), respectiv ely ( section 6.1.2 ). f or simplicity , this counter is being ref erred to as ?rescaler throughout this data sheet. note that the prescaler ma y be used b y either the timer0 module or the wdt , b ut not both. thus , a prescaler assignment f or the timer0 module means that there is no prescaler f or the wdt , and vice-v ersa. the psa and ps2:ps0 bits (option<3:0>) deter mine prescaler assignment and prescale r atio . when assigned to the timer0 module , all instr uctions wr iting to the tmr0 register (e .g., clrf 1, movwf 1, bsf 1,x, etc.) will clear the prescaler . when assigned to wdt , a clrwdt instr uction will clear the prescaler along with the wdt . the prescaler is neither readab le nor wr itab le . on a reset , the prescaler contains all '0's . 6.2.1 switching prescaler assignment the prescaler assignment is fully under softw are control (i.e ., it can be changed ?n the y dur ing prog r am e x ecution). t o a v oid an unintended de vice reset , the f ollo wing instr uction sequence ( example 6-1 ) m ust be e x ecuted when changing the prescaler assignment from timer0 to the wdt . example 6-1: c hanging prescaler (timer0 ? wdt) 1. clrwdt ;clear wdt 2. clrf tmr0 ;clear tmr0 & prescaler 3. movlw '00xx1111? ;these 3 lines (5, 6, 7) 4. option ; are required only if ; desired 5. clrwdt ;ps<2:0> are 000 or 001 6. movlw '00xx1xxx? ;set postscaler to 7. option ; desired wdt rate t o change prescaler from the wdt to the timer0 module , use the sequence sho wn in example 6-2 . this sequence m ust be used e v en if the wdt is disab led. a clrwdt instr uction should be e x ecuted bef ore s witching the prescaler . example 6-2: changing prescaler (wdt ? timer0) clrwdt ;clear wdt and ;prescaler movlw 'xxxx0xxx' ;select tmr0, new ;prescale value and ;clock source option figure 6-6: bloc k dia gram of the timer0/wdt prescaler t0cki t0se pin t cy ( = f osc/4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1mux m m ux w atchdog ti mer psa 0 1 0 1 wdt time- ou t ps2:ps0 8 note: t0 cs , t0 se, psa, ps2:ps0 are bits in the option register . psa wdt enab le bit 0 1 0 1 data bus 8 psa t0cs m u x m u x u x
1998 microchip technology inc. preliminary ds40191a -page 25 pic16cr54c 7.0 special features of the cpu what sets a microcontroller apar t from other processors are special circuits that deal with the needs of real-time applications . the pic16c5x f amily of microcontrollers has a host of such f eatures intended to maximiz e system reliability , minimiz e cost through elimination of e xter nal components , pro vide po w er sa ving oper ating modes and off er code protection. these f eatures are: oscillator selection reset p o w er-on reset (por) de vice reset t imer (dr t) w atchdog timer (wdt) sleep code protection the pic16cr54c f amily has a w a tchdog ti mer which can be shut off only through con gur ation bit wdte. it r uns off of its o wn rc oscillator f or added reliability . there is an 18 ms dela y pro vided b y the de vice reset timer (dr t) , intended to k eep the chip in reset until the cr ystal oscillator is stab le . with this timer on-chip , most applications need no e xter nal reset circuitr y . the sleep mode is designed to off er a v er y lo w current po w er-do wn mode . the user can w ak e up from sleep through e xter nal reset or through a w a tchdog ti mer time-out. se v er al oscillator options are also made a v ailab le to allo w the par t to t the application. the rc oscillator option sa v es system cost while the lp cr ystal option sa v es po w er . a set of con gur ation bits are used to select v ar ious options . 7.1 con guration bits con gur ation bits can be prog r ammed t o select v ar ious de vice con gur ations . t w o bits are f or the selection of the oscillator type and o ne bit is the w atchdog timer enab le bit. nine bits are code protection bits ( figure 7-1 and figure 7-2 ) f or the pic16cr54c de vices . r om de vices ha v e the oscillator con gur ation prog r ammed at the f actor y and these par ts are tested accordingly (see " p roduct identi cation system" diag r ams in the bac k of this data sheet). figure 7-1: c onfiguration w or d f or pic16cr54c cp cp cp cp cp cp cp cp cp wdte f os c1 f os c0 reg ist er : config address (1) : 0fffh bit 11 10 9 8 7 6 5 4 3 2 1 bit0 bit 11- 3: c p: code protection bit s 1 = code protection off 0 = code protection on bit 2: wdte : w atchdog timer enab le bit 1 = wdt enab led 0 = wdt disab led bit 1-0: fosc1:fosc0: oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator note 1: ref er to the pic16c5x prog r amming speci cation (liter ature n umber ds30190) to deter mine ho w to access the con gur ation w ord.
pic16cr54c ds40191a -page 26 preliminary 1998 microchip technology inc. 7.2 oscillator con gurations 7.2.1 oscillator t ypes pic16cr54c s can be oper ated in f our diff erent oscillator modes . the user can prog r am tw o con gur ation bits (fosc1:fosc0) to select one of these f our modes: lp : lo w p o w er cr ystal xt : cr ystal/resonator hs : high speed cr ystal/resonator rc: resistor/capacitor 7.2.2 cr ystal oscillator / cer amic r esonators in xt , lp or hs modes , a cr ystal or cer amic resonator is connected to the osc1 /clkin and osc2 /clk out pins to estab lish oscillation ( figure 7-2 ). t he pic16cr54c oscillator design requires the use of a par allel cut cr ystal. use of a ser ies cut cr ystal ma y giv e a frequency out of the cr ystal man uf acturers speci cations . when in xt , lp or hs modes , the de vice can ha v e an e xter nal cloc k source dr iv e the osc1 /clkin p in ( figure 7-3 ). figure 7-2: cr ystal operation (or ceramic resonator) (hs, xt or lp osc configuration) note 1: see capacitor selection tab les f or recommended v alues of c1 and c2. 2: a ser ies resistor (rs) ma y be required f or a t str ip cut cr ystals . 3: rf v ar ies with the cr ystal chosen (appro x. v alue = 10 m w ). c1 (1) c2 (1) xt al osc2 osc1 rf (3) sleep t o inter nal logic rs (2) pic16cr54c figure 7-3: external cloc k input operation (hs, xt or lp osc configuration) t ab le 7-1: capacitor selection for ceramic resonator s - pic16cr54c t ab le 7-2: capacitor selection for cr ystal oscillator - pic16cr54c osc t ype resonator freq cap. rang e c1 cap. rang e c2 xt 455 kh z 2.0 mhz 4.0 mhz 68-100 pf 15- 33 p f 10- 22 p f 68-100 pf 15- 33 p f 10- 22 p f hs 8.0 mhz 16.0 mh z 10- 22 p f 10 p f 10- 22 p f 10 p f these v alues are f or design guidance only . since each resonator has its o wn char acter istics , the user should consult the resonator man uf acturer f or appropr iate v alues of e xter nal components . osc t ype resonator freq cap.rang e c1 cap. rang e c2 lp 32 khz (1) 15 pf 15 pf xt 100 khz 200 khz 455 khz 1 mhz 2 mhz 4 mhz 15-30 pf 15-30 pf 15-30 pf 15-30 pf 15 pf 15 pf 200-300 pf 100-200 pf 15-100 pf 15-30 pf 15 pf 15 pf hs 4 mhz 8 mh z 20 mhz 15 p f 15 pf 15 pf 15 p f 15 p f 15 pf note 1: f or v dd > 4.5v , c1 = c2 ? 30 pf is recommended. t hese v alues are f or design guidance only . rs ma y be required in hs mode as w ell as xt mode to a v oid o v erdr iving cr ystals with lo w dr iv e le v el speci cation. since each cr ystal has its o wn char acter istics , the user should consult the cr ystal man uf acturer f or appropr iate v alues of e xter nal components . note: if y ou c hang e fr om this de vice to another de vice , please verify oscillator c haracteristics in y our application. cloc k from e xt. system osc1 osc2 pic16cr54c open
1998 microchip technology inc. preliminary ds40191a -page 27 pic16cr54c 7.2.3 exter nal cr ystal oscillator circuit either a prepac kaged oscillator o r a simple oscillator circuit with ttl gates can be used as an e xter nal cr ystal oscillator circuit. p repac kaged oscillators pro vide a wide oper ating r ange and better stability . a w ell-designed cr ystal oscillator will pro vide good perf or mance with ttl gates . t w o types of cr ystal oscillator circuits can be used: one with par allel r esonance , or one with ser ies r esonance . figure 7-4 sho ws implementation of a par allel resonant oscillator circuit. the circuit is designed to use the fundamental frequency of the cr ystal. the 74as04 in v er ter perf or ms the 180-deg ree phase shift that a par allel oscillator requires . the 4.7 k w resistor pro vides the negativ e f eedbac k f or stability . the 10 k w potentiometers bias the 74as04 in the linear region. this circuit could be used f or e xter nal oscillator designs . figure 7-4: external p arallel resonant cr ystal oscillator cir cuit (using xt , hs or lp oscillator mode) figure 7-5 sho ws a ser ies resonant oscillator circuit. this circuit is also designed to use the fundamental frequency of the cr ystal. the in v er ter perf or ms a 180-deg ree phase shift in a ser ies resonant oscillator circuit. the 330 w resistors pro vide the negativ e f eedbac k to bias the in v er ters in their linear region. note: if y ou c hang e fr om this de vice to another de vice , please verify oscillator c haracteristics in y our application. 20 pf +5v 20 pf 10k 4.7k 10k 74as04 xt al 10k 74as04 pic16cr54c clkin t o other de vices osc2 100k figure 7-5: external series resonant cr ystal oscillator cir cuit (using xt , hs or lp oscillator mode) 7.2.4 rc oscillator f or timing insensitiv e applications , the rc de vice option off ers additional cost sa vings . the rc oscillator frequency is a function of the supply v oltage , the resistor (re xt) and capacitor (ce xt) v alues , and the oper ating temper ature . in addition to this , the oscillator frequency will v ar y from unit to unit due to nor mal process par ameter v ar iation. fur ther more , the diff erence in lead fr ame capacitance betw een pac kage types will also aff ect the oscillation frequency , especially f or lo w ce xt v alues . the user also needs to tak e into account v ar iation due to toler ance of e xter nal r and c components used. figure 7-6 sho ws ho w the r/c combination is connected to the pic16cr54c . f or re xt v alues belo w 2.2 k w , the oscillator oper ation ma y become unstab le , or stop completely . f or v er y high re xt v alues (e .g. , 1 m w ) t he oscillator becomes sensitiv e to noise , humidity and leakage . thus , w e recommend k eeping re xt betw een 3 k w and 100 k w . although the oscillator will oper ate with no e xter nal capacitor (ce xt = 0 pf), w e recommend using v alues abo v e 20 pf f or noise and stability reasons . with no or small e xter nal capacitance , the oscillation frequency can v ar y dr amatically due to changes in e xter nal capacitances , such as pcb tr ace capacitance or pac kage lead fr ame capacitance . note: if y ou c hang e fr om this de vice to another de vice , please verify oscillator c haracteristics in y our application. 330 74as04 74as04 pic16cr54c clkin t o other de vices xt al 330 74as04 0.1 m f osc2 100k
pic16cr54c ds40191a -page 28 preliminary 1998 microchip technology inc. the electr ical speci cations sections sho w rc frequency v ar iation from par t to par t due to nor mal process v ar iation. the v ar iation is larger f or larger r (since leakage current v ar iation will aff ect rc frequency more f or large r) and f or smaller c (since v ar iation of input capacitance will aff ect rc frequency more). also , see the electr ical speci cations sections f or v ar iation of oscillator frequency due to v dd f or giv en re xt/ce xt v alues as w ell as frequency v ar iation due to oper ating temper ature f or giv en r, c , and v dd v alues . t he oscillator frequency , divided b y 4, is a v ailab le on the osc2/clk out pin, and can be used f or test pur poses or to synchroniz e other logic. figure 7-6: rc oscillator mode note: if y ou c hang e fr om this de vice to another de vice , please verify oscillator c haracteristics in y our application. v dd re xt ce xt v ss osc1 inter nal cloc k osc2/clk out f osc/4 pic1 6 cr54c n 7.3 reset pic16cr54c de vices ma y be reset in one of the f ollo wing w a ys: p o w er- on reset (por) m clr reset (n or mal oper ation ) mclr w ak e-up reset (from sleep) w dt r eset (nor mal oper ation) wdt w ak e-up reset (from sleep) t ab le 7-3 sho ws these reset conditions f or the pcl a nd st a tus r egisters . some registers are not aff ected in an y reset condition. their status is unkno wn on por and unchanged in an y other reset. most other registers are reset to a ?eset state on p o w er-on reset (por), mclr or wdt reset. a mclr or wdt w ak e-up from sleep also results in a de vice reset, and not a contin uation of oper ation bef ore sleep . the t o and pd bits (st a tus <4:3>) are set or cleared depending on the diff erent reset conditions ( section 7.7 ). these bits ma y be used to deter mine the nature of the reset. t ab le 7-4 lists a full descr iption of reset states of all registers . figure 7-7 sho ws a simpli ed b loc k diag r am of the on-chip reset circuit .
pic16cr54c ds40191a -page 29 preliminary 1998 microchip technology inc. t ab le 7-3: reset conditions f or special register s t ab le 7-4: reset conditions f or all register s figure 7-7: simplified bloc k dia gram of on-chip reset cir cuit condition pcl ad dr: 02h st a tus ad dr: 03h p o w er-on reset 1111 1111 0001 1xxx mclr reset (nor mal oper ation) 1111 1111 000u uuuu (1) mclr w ak e-up (from sleep) 1111 1111 0001 0uuu wdt reset (nor mal oper ation) 1111 1111 0000 1uuu (2) wdt w ak e-up (from sleep) 1111 1111 0000 0uuu legend: u = unchanged, x = unkno wn, - = unimplemented read as '0'. note 1: t o and pd bits retain their last v alue until one of the other reset conditions occur . 2: the clrwdt instr uction will set the t o and pd bits . register ad dress p o wer -on reset mclr or wdt reset w n/a xxxx xxxx uuuu uuuu tris n/a 1111 1111 1111 1111 option n/a --11 1111 --11 1111 indf 00h xxxx xxxx uuuu uuuu tmr0 01h xxxx xxxx uuuu uuuu pcl (1) 02h 1111 1111 1111 1111 st a tus (1) 03h 0001 1xxx 000q quuu fsr 04h 111x xxxx 111u uuuu por t a 05h ---- xxxx ---- uuuu por tb 06h xxxx xxxx uuuu uuuu gener al pur pose register files 07-1fh xxxx xxxx uuuu uuuu legend: u = unchanged, x = unkno wn, - = unimplemented, read as '0', q = s ee tab les in section 7.7 f or possib le v alues . note 1: see t ab le 7-3 f or reset v alue f or speci c conditions . 8-bit asynch ripple counter (star t-up timer) s q r q v dd mclr / v pp pin p o w er-up detect on-chip rc osc por (p o w er-on reset) wdt time-out reset chip reset wdt
pic16cr54c ds40191a -page 30 preliminary 1998 microchip technology inc. 7.4 p o wer -on reset (por) the pic16cr54c incor por ates o n -c hip p o w er-on reset (por) circuitr y which pro vides an inter nal chip reset f or most po w er-up situations . t o use this f eature , the user merely t ie s the mclr /v pp pin to v dd . a simpli ed b loc k diag r am of the on-chip p o w er-on reset circuit is sho wn in figure 7-7 . t he p o w er-on reset circuit and the de vice reset timer ( section 7.5 ) circuit are closely related. o n po w er-up , the reset latch is set and the dr t is reset. the dr t timer begins counting once it detects mclr to be high. after the time-out per iod, which is typically 18 ms , it will reset the reset l atch and thus end the on-chip reset signal. a po w er-up e xample where mclr is not tied to v dd is sho wn in figure 7-9 . v dd is allo w ed to r ise and stabiliz e bef ore br inging mclr high. the chip will actually come out of reset t drt msec after mclr goes high . in figure 7-10 , the on-chip p o w er-on reset f eature is being used ( mclr and v dd are tied together). the v dd is stab le bef ore the star t-up timer times out and there is no prob lem in getting a proper reset. ho w e v er , figure 7-11 depicts a prob lem situation where v dd r ises too slo wly . the time betw een when the dr t senses a high on the mclr / v pp pin , and when the mclr / v pp pin (and v dd ) actually reach their full v alue , is too long. in this situation, when the star t-up timer times out, v dd has not reached the v dd (min) v alue and the chip is , theref ore , not guar anteed to function correctly . f or such situations , w e recommend that e xter nal rc circuits be used to achie v e longer por dela y times ( figure 7-8 ). f or more inf or mation on pic16cr54c por, see p o w er-up consider ations - an522 in the embedded control handbook . the por circuit does not produce an inter nal reset when v dd declines . note: when the de vice star ts nor mal oper ation (e xits the reset condition), de vice oper at- ing par ameters (v oltage , frequency , tem- per ature , etc.) m ust be meet to ensure oper ation. if these conditions are not met, the de vice m ust be held in reset until the oper ating conditions are met. figure 7-8: exter n al p o wer -on reset cir cuit (for slo w v dd p o wer -up) c r1 r d mclr pic16cr54c v dd v dd e xter nal p o w er-on reset circuit is required only if v dd po w er-up is too slo w . the diode d helps discharge the capacitor quic kly when v dd po w ers do wn. r < 40 k w is recommended to mak e sure that v oltage drop across r does not violate the de vice electr ical speci cation. r1 = 100 w to 1 k w will limit an y current o wing into mclr from e xter nal capacitor c in the e v ent of mclr pin breakdo wn due to electrostatic discharge (esd) or electr ical ov erstress (eos).
pic16cr54c ds40191a -page 31 preliminary 1998 microchip technology inc. figure 7-9: t ime-out sequence on p o wer -up ( mclr not tied to v dd ) figure 7-10: t ime-out sequence on p o wer -up ( mclr tied to v dd ) : f ast v dd rise time figure 7-11: time-out sequence on p o wer -up ( mclr tied to v dd ): slo w v dd rise time v dd mclr internal por dr t time-out internal reset t dr t v dd mclr internal por dr t time-out internal reset t dr t v dd mclr internal por dr t time-out internal reset t dr t v 1 when v dd r ises slo wly , the t drt time-out e xpires long bef ore v dd has reached its nal v alue . in this e xample , the chip will reset proper ly if , and only if , v1 3 v dd min
pic16cr54c ds40191a -page 32 preliminary 1998 microchip technology inc. 7.5 de vice reset timer (dr t) the de vice reset timer (dr t) pro vides a x ed 18 ms nominal time-out on reset. the dr t oper ates on an inter nal rc oscillator . the processor is k ept in reset as long as the dr t is activ e . the dr t dela y allo ws v dd to r ise abo v e v dd min., and f or the oscillator to stabiliz e . oscillator circuits based on cr ystals or cer amic resonators require a cer tain time after po w er-up to estab lish a stab le oscillation. the on-chip dr t k eeps the de vice in a reset condition f or appro ximately 18 ms after the v oltage on the mclr / v pp pin has reached a logic high (v ih ) le v el. thus , e xter nal rc netw or ks connected to the mclr input are not required in most cases , allo wing f or sa vings in cost-sensitiv e and/or space restr icted applications . the de vice reset time dela y will v ar y from chip to chip due to v dd , temper ature , and process v ar iation. see a c par ameters f or details . the dr t will also be tr iggered upon a w atchdog timer time-out. this is par ticular ly impor tant f or applications using the wdt to w ak e the pic16cr54c from sleep mode automatically . 7.6 w atc hdog timer (wdt) the w atchdog timer (wdt) is a free r unning on-chip rc oscillator which does not require an y e xter nal components . this rc oscillator is separ ate from the rc oscillator of the osc1/clkin pin. that means that the wdt will r un e v en if the cloc k on the osc1/clkin and osc2/clk out pins ha v e been stopped, f or e xample , b y e x ecution of a sleep instr uction. dur ing nor mal oper ation or sleep , a wdt reset or w ak e-up reset gener ates a de vice reset . the t o bit (st a tus<4>) will be cleared upon a w atchdog timer reset. the wdt can be per manently disab led b y prog r amming the con gur ation bit wdte as a '0' ( section 7.1 ). ref er to the pic16c5x prog r amming speci cations (liter ature number ds30190) to deter mine ho w to access the con gur ation w ord. 7.6.1 wdt p er iod the wdt has a nominal time-out per iod of 18 ms , (with no prescaler). if a longer time-out per iod is desired, a prescaler with a division r atio of up to 1:128 can be assigned to the wdt (under softw are control) b y wr iting to the option register . thus , time-out a per iod of a nominal 2.3 seconds can be realiz ed. these per iods v ar y with temper ature , v dd and par t-to-par t process v ar iations (see dc specs). under w orst case conditions ( v dd = min., t emper ature = max., max. wdt prescaler), it ma y tak e se v er al seconds bef ore a wdt time-out occurs . 7.6.2 wdt prog r amming considerations the clrwdt instr uction clears the wdt and the postscaler , if assigned to the wdt , and pre v ents it from timing out and gener ating a de vice reset . the sleep instr uction resets the wdt and the postscaler , if assigned to the wdt . this giv es the maxim um sleep time bef ore a wdt w ak e-up reset.
pic16cr54c ds40191a -page 33 preliminary 1998 microchip technology inc. figure 7-12: w atc hdog timer bloc k dia gram t ab le 7-5: summar y of register s associated with the w atc hdog timer ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on p o wer -on reset v alue on mclr and wdt reset n/a option t0cs t0se psa ps2 ps1 ps0 --11 1111 --11 1111 legend: shaded b o x es = not used b y w atchdog timer , = unimplemented, read as '0', u = unchange d 1 0 1 0 f rom tmr 0 cloc k sourc e t o tmr0 p ostscaler wdt enab le epr om bit psa wdt time-out ps2:ps0 psa mux 8 - to - 1 mux p ostscaler m u x w atchdog timer note: t0cs , t0se, psa, ps2:ps0 are bits in the option register .
pic16cr54c ds40191a -page 34 preliminary 1998 microchip technology inc. 7.7 time-out sequence and p o wer do wn status bits ( t o / pd ) the t o and pd bits in the st a tus register can be tested to deter mine if a reset condition has been caused b y a po w er-up condition, a mclr or w atchdog timer (wdt) reset, or a mclr or wdt w ak e-up reset. these st a tus bits are only aff ected b y e v ents listed in t ab le 7-7 . t ab le 7-3 lists the reset conditions f or the special function registers , while t ab le 7-4 lists the reset conditions f or all the registers . t ab le 7-6: t o / pd status after reset t o pd reset was caused b y 1 1 p o w er-up (por) u u mclr reset (nor mal oper ation) (1) 1 0 mclr w ak e-up reset ( from sleep ) 0 1 wdt reset (nor mal oper ation) 0 0 wdt w ak e-up reset ( from sleep ) legend: u = unchanged note 1: the t o and pd bit s maintain their status ( u ) until a reset occurs . a lo w-pulse on the mclr input does not change the t o and pd status bits . t ab le 7-7: events aff ecting t o / pd status bits event t o pd remarks p o w er-up 1 1 wdt time - out 0 u no eff ect on pd sleep instr uction 1 0 clrwdt instr uction 1 1 legend: u = unchanged a wdt time - out will occur regardless of the status of the t o bit. a sleep instr uction will be e x ecuted, regardless of the status of the pd bit. t ab le 7-6 re ects the status of t o and pd after the corresponding e v ent. 7.8 reset on br o wn-out a bro wn-out is a condition where de vice po w er (v dd ) dips belo w its minim um v alue , b ut not to z ero , and then reco v ers . the de vice should be reset in the e v ent of a bro wn-out. t o reset pic16 cr54c de vices when a bro wn-out occurs , e xter nal bro wn-out protection circuits ma y be b uilt, as sho wn in figure 7-13 and figure 7-14 . figure 7-13: br o wn-out pr otection cir cuit 1 figure 7-14: br o wn-out pr otection cir cuit 2 this circuit will activ ate reset when v dd goes belo w vz + 0.7v (w here vz = zener v oltage ) . 33k 10k 40k v dd mclr pic16cr54c v dd q1 t his bro wn-out circuit is less e xpensiv e , although less accur ate . t r ansistor q1 tur ns off when v dd is belo w a cer tain le v el such that: v dd r1 r1 + r2 = 0.7v r2 40k v dd mclr pic16cr54c r1 q1 v dd
1998 microchip technology inc. preliminary ds40191a -page 35 pic16cr54c 7.9 p o wer -do wn mode (sleep) a de vice ma y be po w ered do wn (sleep) and later po w ered up (w ak e-up from sleep). 7.9.1 sleep the p o w er-do wn mode is entered b y e x ecuting a sleep instr uction. if enab led, the w atchdog timer will be cleared b ut k eeps r unning, the t o bit (st a tus<4>) is set, the pd bit (st a tus<3>) is cleared a nd the oscillator dr iv er is tur ned off . the i/o por ts maintain the status the y had bef ore the sleep instr uction w as e x ecuted (dr iving high, dr iving lo w , or hi-imped an ce) . it should be noted that a r eset gener ated b y a wdt time-out does not dr iv e the mclr /v pp pin lo w . f or lo w est current consumption while po w ered do wn, the t0cki input should be at v dd or v ss and the mclr /v pp pin m ust be at a logic high le v el ( v ih mclr ). 7.9.2 w ak e-up from sleep the de vice can w ak e up from sleep through one of the f ollo wing e v ents: 1. an e x ter nal reset input on mclr / v pp pin . 2. a w atchdog ti mer time-out reset (if wdt w as enab led) . both of these e v ents cause a de vice reset. the t o and pd bits can be used to deter mine the cause of de vice reset. the t o bit is cleared if a wdt time-out occurred (and caused w ak e-up). the pd bit, which is set on po w er-up , is cleared when sleep is in v ok ed. the wdt is cleared when the de vice w ak es from sleep , regardless of the w ak e-up source . 7.10 pr ogram v eri cation/ code pr otectio n if the code protection bit(s) ha v e not been prog r ammed, the on-chip prog r am memor y can be read out f or v er i cation pur poses . note: microchip does not recommend code pro- tecting windo w ed de vices .
pic16cr54c ds40191a -page 36 preliminary 1998 microchip technology inc. notes:
1998 microchip technology inc. preliminary ds40191a -page 37 pic16cr54c 8.0 instruction set summar y each pic16cr54c instr uction is a 12-bit w ord divided into an opcode, which speci es the instr uction type , and one or more oper ands which fur ther specify the oper ation of the instr uction. the pic16cr54c instr uction set summar y in t ab le 8-2 g roups the instr uctions into b yte-or iented, bit-or iented, and liter al and control oper ations . t ab le 8-1 sho ws the opcode eld descr iptions . f or b yte-oriented instr uctions , 'f' represents a le register designator and 'd' represents a destination designator . the le register designator is used to specify which one of the 32 le registers is to be used b y the instr uction. the destination designator speci es where the result of the oper ation is to be placed. if 'd' is '0', the result is placed in the w register . if 'd' is '1', the result is placed in the le register speci ed in the instr uction. f or bit-oriented instr uctions , 'b' represents a bit eld designator which selects the n umber of the bit aff ected b y the oper ation, while 'f' represents the n umber of the le in which the bit is located. f or literal and contr ol oper ations , 'k' represents an 8 o r 9-bit constant or liter al v alue . t ab le 8-1: opcode field de scriptions field description f register le address (0x00 to 0x7f) w w or king register (accum ulator) b bit address within an 8-bit le register k liter al eld, constant data or label x don't care location (= 0 or 1) the assemb ler will gener ate code with x = 0. it is the recommended f or m of use f or compatibility with all microchip softw are tools . d destination select; d = 0 (store result in w) d = 1 (store result in le register 'f' ) d ef ault is d = 1 label label name tos t op of stac k pc prog r am counter wdt w atchdog timer counter to time-out bit pd p o w er-do wn bit dest destination, either the w register or the speci ed register le location [ ] options ( ) contents ? assigned to < > register bit eld ? in the set of i talics user de ned ter m (f ont is cour ier) a ll instr uctions are e x ecuted within one single instr uction cycle , unless a conditional test is tr ue or the prog r am counter is changed as a result of an instr uction. in this case , the e x ecution tak es tw o instr uction cycles . one instr uction cycle consists of f our oscillator per iods . thus , f or an oscillator frequency of 4 mhz, the nor mal instr uction e x ecution time is 1 m s . if a conditional test is tr ue or the prog r am counter is changed as a result of an instr uction, the instr uction e x ecution time is 2 m s . figure 8-1 sho ws the three gener al f or mats that the instr uctions can ha v e . a ll e xamples in the gure use the f ollo wing f or mat to represent a he xadecimal n umber : 0xhh h where ' h ' signi es a he xadecimal digit. figure 8-1: g eneral format f or instructions byte-oriented le register oper ations 1 1 6 5 4 0 d = 0 f or destination w opcode d f (file #) d = 1 f or destination f f = 5- bit le register address bit-oriented le register oper ations 1 1 8 7 5 4 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 5- bit le register address literal and contr ol oper ations (e xcept goto ) 1 1 8 7 0 opcode k ( liter al) k = 8-bit immediate v alue literal and contr ol oper ations - goto instr uction 1 1 9 8 0 opcode k ( liter al) k = 9- bit immediate v alue
pic16cr54c ds40191a -page 38 preliminary 1998 microchip technology inc. t ab le 8-2: instruction set summar y mnemonic, operands description cyc les 12-bit opcode status aff ected notes msb lsb add wf and wf clrf clr w comf decf decfsz incf incfsz ior wf mo vf mo vwf nop rlf rrf subwf sw apf xor wf f ,d f ,d f f , d f , d f , d f , d f , d f , d f , d f f , d f , d f , d f , d f , d add w and f and w with f clear f clear w complement f decrement f decrement f , skip if 0 increment f increment f , skip if 0 inclusiv e or w with f mo v e f mo v e w to f no oper ation rotate left f through carr y rotate r ight f through carr y subtr act w from f sw ap f exclusiv e or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 0001 0001 0000 0000 0010 0000 0010 0010 0011 0001 0010 0000 0000 0011 0011 0000 0011 0001 11df 01df 011f 0100 01df 11df 11df 10df 11df 00df 00df 001f 0000 01df 00df 10df 10df 10df ffff ffff ffff 0000 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c ,dc ,z z z z z z none z none z z none none c c c ,dc ,z none z 1,2,4 2,4 4 2,4 2,4 2,4 2,4 2,4 2,4 1,4 2,4 2,4 1,2,4 2,4 2,4 bit -oriented file register opera tions bcf bsf btfsc btfss f , b f , b f , b f , b bit clear f bit set f bit t est f , skip if clear bit t est f , skip if set 1 1 1 (2) 1 (2) 0100 0101 0110 0111 bbbf bbbf bbbf bbbf ffff ffff ffff ffff none none none none 2,4 2,4 literal and contr ol opera tions andl w call clr wdt go t o iorl w mo vl w option retl w sleep tris xorl w k k k k k k k k f k and liter al with w call subroutine clear w a tchdog ti mer unconditional br anch inclusiv e or li ter al with w mo v e liter al to w load option register retur n, place li ter al in w go into standb y mode load tris register exclusiv e or liter al to w 1 2 1 2 1 1 1 2 1 1 1 1110 1001 0000 101k 1101 1100 0000 1000 0000 0000 1111 kkkk kkkk 0000 kkkk kkkk kkkk 0000 kkkk 0000 0000 kkkk kkkk kkkk 0100 kkkk kkkk kkkk 0010 kkkk 0011 0fff kkkk z none t o , pd none z none none none t o , pd none z 1 3 note 1: the 9th bit of the prog r am counter will be f orced to a '0' b y an y instr uction that wr ites to the pc e xcept f or goto . ( see individual de vice data sheets , memor y section/indirect data addressing, indf and fsr registers) 2: when an i/o register is modi ed as a function of itself (e .g. movf portb, 1 ), the v alue used will be that v alue present on the pins themselv es . f or e xample , if the data latch is '1' f or a pin con gured as input and is dr iv en lo w b y an e xter nal de vice , the data will be wr itten bac k with a '0'. 3: the instr uction tris f , where f = 5 or 6 causes the contents of the w register to be wr itten to the tr istate latches of por t a or b respectiv ely . a '1' f orces the pin to a hi-impedance state and disab les the output b uff- ers . 4: if this instr uction is e x ecuted on the tmr0 register (and, where applicab le , d = 1), the prescaler will be cleared (if assigned to tmr0).
1998 microchip technology inc. preliminary ds40191a -page 39 pic16cr54c add wf ad d w and f syntax: [ label ] add wf f ,d oper ands: 0 f 31 d ? [0,1] oper ation: (w) + (f) ? (dest) status aff ected: c , dc , z encoding: 0001 11df ffff descr iption: add the contents of the w register and register 'f'. if 'd' is 0 the result is stored in the w register . if 'd' is ' 1 ' the result is stored bac k in register 'f' . w ords: 1 cycles: 1 example: addwf fsr , 0 b ef ore instr uction w = 0x17 fsr = 0xc2 after instr uction w = 0xd9 fsr = 0xc2 andl w and li teral with w syntax: [ label ] andl w k oper ands: 0 k 255 oper ation: (w) . and . (k) ? (w) status aff ected: z encoding: 1110 kkkk kkkk descr iption: the contents of the w register are and?d with the eight -b it liter al 'k'. the result is placed in the w register . w ords: 1 cycles: 1 example: andlw 0x5f b ef ore instr uction w = 0xa3 after instr uction w = 0x03 and wf and w with f syntax: [ label ] and wf f ,d oper ands: 0 f 31 d ? [0,1] oper ation: (w) .and . (f) ? (dest) status aff ected: z encoding: 0001 01df ffff descr iption: the contents of the w register are and?d with register 'f'. if 'd' is 0 the result is stored in the w register . if 'd' is ' 1 ' the result is stored bac k in register 'f' . w ords: 1 cycles: 1 example: andwf fsr, 1 b ef ore instr uction w = 0x17 fsr = 0xc2 after instr uction w = 0x17 fsr = 0x02 bcf bit clear f syntax: [ label ] bcf f ,b oper ands: 0 f 31 0 b 7 oper ation: 0 ? ( f < b> ) status aff ected: none encoding: 0100 bbbf ffff descr iption: bit 'b' in register 'f' is cleared. w ords: 1 cycles: 1 example: bcf flag_reg, 7 b ef ore instr uction fla g_reg = 0xc7 after instr uction fla g_reg = 0x47
pic16cr54c ds40191a -page 40 preliminary 1998 microchip technology inc. bsf bit set f syntax: [ label ] bsf f ,b oper ands: 0 f 31 0 b 7 oper ation: 1 ? ( f ) status aff ected: none encoding: 0101 bbbf ffff descr iption: bit 'b' in register 'f' is set. w ords: 1 cycles: 1 example: bsf flag_reg, 7 b ef ore instr uction fla g_reg = 0x0a after instr uction fla g_reg = 0x8a btfsc b it t est f , sk ip if clear syntax: [ label ] btfsc f ,b oper ands: 0 f 31 0 b 7 oper ation: skip if (f) = 0 status aff ected: none encoding: 0110 bbbf ffff descr iption: if bit 'b' in register 'f' is 0 t hen the ne xt instr uction is skipped. if bit 'b' is 0 t hen the ne xt instr uction f etched dur ing the current instr uction e x ecution is discarded, and a n nop is e x ecuted instead, making this a 2 cycle instr uction. w ords: 1 cycles: 1(2) example: here false true btfsc goto flag,1 process_code b ef ore instr uction pc = address (here) after instr uction if fla g<1> = 0, pc = address (true) ; if fla g<1> = 1, pc = a ddress (false) btfss bit t est f , sk ip if set syntax: [ label ] btfss f ,b oper ands: 0 f 31 0 b < 7 oper ation: skip if (f) = 1 status aff ected: none encoding: 0111 bbbf ffff descr iption: if bit 'b' in register 'f' is '1' then the ne xt instr uction is skipped. if bit 'b' is '1', then the ne xt instr uction f etched dur ing the current instr uction e x ecution, is discarded and a n nop is e x ecuted instead, making this a 2 cycle instr uction. w ords: 1 cycles: 1 (2) example: here btfss flag,1 false goto process_code true bef ore instr uction pc = address (here) after instr uction if fla g<1> = 0, pc = address (false) ; if fla g<1> = 1, pc = address (true)
1998 microchip technology inc. preliminary ds40191a -page 41 pic16cr54c call subr outine call syntax: [ label ] call k oper ands: 0 k 2 55 oper ation: (pc) + 1 ? t op of stac k; k ? pc< 7: 0> ; ( st a tus<6:5>) ? pc<10:9> ; 0 ? pc<8> status aff ected: none encoding: 1001 kkkk kkkk descr iption: subroutine call. first, retur n address (pc+1) is pushed onto the stac k. the eight bit immediate address is loaded into pc bits < 7 :0>. the upper bits pc <10:9> a re loaded from st a- tus<6:5>, pc<8> is cleared. call is a tw o cycle instr uction. w ords: 1 cycles: 2 example: here call there b ef ore instr uction pc = ad dress (here) after instr uction pc = ad dress (there) t os = ad dress (here + 1 ) clrf clear f syntax: [ label ] clrf f oper ands: 0 f 31 oper ation: 00h ? ( f ); 1 ? z status aff ected: z encoding: 0000 011f ffff descr iption: the contents of register 'f' are cleared and the z bit is set. w ords: 1 cycles: 1 example: clrf flag_reg b ef ore instr uction fla g_reg = 0x5a after instr uction fla g_reg = 0x00 z = 1 clr w clear w syntax: [ label ] clr w oper ands: none oper ation: 00h ? (w) ; 1 ? z status aff ected: z encoding: 0000 0100 0000 descr iption: the w register i s cleared. zero bit (z) is set. w ords: 1 cycles: 1 example: clrw b ef ore instr uction w = 0x5a after instr uction w = 0x00 z = 1 clr wdt clear w atc hdog timer syntax: [ label ] clr wdt oper ands: none oper ation: 00h ? wdt ; 0 ? wdt prescaler (if assigned) ; 1 ? t o; 1 ? pd status aff ected: t o , pd encoding: 0000 0000 0100 descr iption: the clrwdt i nstr uction resets the wdt . it also resets the prescaler , if the prescaler is assigned to the wdt and not timer0. status bits t o and pd are set. w ords: 1 cycles: 1 example: clrwdt b ef ore instr uction wdt counter = ? after instr uction wdt counter = 0x00 wdt prescale = 0 t o = 1 pd = 1
pic16cr54c ds40191a -page 42 preliminary 1998 microchip technology inc. comf complement f syntax: [ label ] comf f ,d oper ands: 0 f 31 d ? [0,1] oper ation: ( f ) ? (dest) status aff ected: z encoding: 0010 01df ffff descr iption: the contents of register 'f' are comple- mented. if 'd' is 0 the result is stored in the w register . if 'd' is 1 the result is stored bac k in register 'f'. w ords: 1 cycles: 1 example: comf reg1,0 b ef ore instr uction reg1 = 0x13 after instr uction reg1 = 0x13 w = 0xec decf decrement f syntax: [ label ] decf f ,d oper ands: 0 f 31 d ? [0,1] oper ation: (f) ?1 ? (dest) status aff ected: z encoding: 0000 11df ffff descr iption: decrement register 'f'. if 'd' is 0 the result is stored in the w register . if 'd' is 1 the result is stored bac k in register 'f'. w ords: 1 cycles: 1 example: decf cnt, 1 b ef ore instr uction cnt = 0x01 z = 0 after instr uction cnt = 0x00 z = 1 decfsz decrement f , sk ip if 0 syntax: [ label ] decfsz f ,d oper ands: 0 f 31 d ? [0,1] oper ation: (f) ?1 ? d; s kip if result = 0 status aff ected: none encoding: 0010 11df ffff descr iption: the contents of register 'f' are decre- mented. if 'd' is 0 the result is placed in the w register . if 'd' is 1 the result is placed bac k in register 'f'. if the result is 0, the ne xt instr uction, which is already f etched, is discarded and an n op is e x ecuted instead mak- ing it a tw o cycle instr uction. w ords: 1 cycles: 1(2) example: here decfsz cnt, 1 goto loop continue b ef ore instr uction pc = address (here) after instr uction cnt = cnt - 1; if cnt = 0, pc = addres s (continue) ; if cnt 1 0, pc = addres s (here+1) go t o unconditional branc h syntax: [ label ] go t o k oper ands: 0 k 511 oper ation: k ? pc<8:0>; st a tus<6:5> ? pc<10:9> status aff ected: none encoding: 101k kkkk kkkk descr iption: goto is an unconditional br anch. the 9-b it immediate v alue is loaded into pc bits < 8 :0>. the upper bits of pc are loaded from st a tus < 6 : 5 >. goto is a tw o cycle instr uction. w ords: 1 cycles: 2 example: goto there a fter instr uction pc = address (there)
1998 microchip technology inc. preliminary ds40191a -page 43 pic16cr54c incf increment f syntax: [ label ] incf f ,d oper ands: 0 f 31 d ? [0,1] oper ation: (f) + 1 ? (dest) status aff ected: z encoding: 0010 10df ffff descr iption: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in the w register . if 'd' is 1 the result is placed bac k in register 'f'. w ords: 1 cycles: 1 example: incf cnt, 1 b ef ore instr uction cnt = 0xff z = 0 after instr uction cnt = 0x00 z = 1 incfsz increment f , sk ip if 0 syntax: [ label ] incfsz f ,d oper ands: 0 f 31 d ? [0,1] oper ation: (f) + 1 ? (dest), skip if result = 0 status aff ected: none encoding: 0011 11df ffff descr iption: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in the w register . if 'd' is 1 the result is placed bac k in register 'f'. if the result is 0, then the ne xt instr uc- tion, which is already f etched, is dis- carded and an n op is e x ecuted instead making it a tw o cycle instr uc- tion. w ords: 1 cycles: 1(2) example: here incfsz cnt, 1 goto loop continue b ef ore instr uction pc = address (here) after instr uction cnt = cnt + 1; if cnt = 0 , pc = addres s (continue) ; if cnt 1 0 , pc = addres s (here +1) iorl w inc lusive or li teral with w syntax: [ label ] iorl w k oper ands: 0 k 255 oper ation: (w) .or. (k) ? (w) status aff ected: z encoding: 1101 kkkk kkkk descr iption: the contents of the w register are or?d with the eight bit liter al 'k'. the result is placed in the w register . w ords: 1 cycles: 1 example: iorlw 0x35 b ef ore instr uction w = 0x9a after instr uction w = 0xbf z = 0 ior wf inc lusive or w with f syntax: [ label ] ior wf f ,d oper ands: 0 f 31 d ? [0,1] oper ation: (w) . or. (f) ? (dest) status aff ected: z encoding: 0001 00df ffff descr iption: inclusiv e or the w register with regis- ter 'f'. if 'd' is 0 the result is placed in the w register . if 'd' is 1 the result is placed bac k in register 'f'. w ords: 1 cycles: 1 example: iorwf result, 0 b ef ore instr uction resul t = 0x13 w = 0x91 after instr uction resul t = 0x13 w = 0x93 z = 0
pic16cr54c ds40191a -page 44 preliminary 1998 microchip technology inc. mo vf mo ve f syntax: [ label ] mo vf f ,d oper ands: 0 f 31 d ? [0,1] oper ation: (f) ? (dest) status aff ected: z encoding: 0010 00df ffff descr iption: the contents of register ' f ' is mo v ed to destination ' d ' . if ' d ' is 0 , destination is the w register . if ' d ' is 1 , the destination is le register ' f '. ' d ' is 1 is useful to test a le register since status ag z is aff ected. w ords: 1 cycles: 1 example: movf fsr, 0 a fter instr uction w = v alue in fsr register mo vl w mo ve literal to w syntax: [ label ] mo vl w k oper ands: 0 k 255 oper ation: k ? (w) status aff ected: none encoding: 1100 kkkk kkkk descr iption: the eight bit liter al 'k' is loaded into the w register . the don? cares will assem- b le as 0s . w ords: 1 cycles: 1 example: movlw 0x5a a fter instr uction w = 0x5a mo vwf mo ve w to f syntax: [ label ] mo vwf f oper ands: 0 f 31 oper ation: (w) ? (f) status aff ected: none encoding: 0000 001f ffff descr iption: mo v e data from the w register to regis- ter 'f' . w ords: 1 cycles: 1 example: movwf temp_reg b ef ore instr uction temp_reg = 0xff w = 0x4f after instr uction temp_reg = 0x4f w = 0x4f nop no operation syntax: [ label ] nop oper ands: none oper ation: no oper ation status aff ected: none encoding: 0000 0000 0000 descr iption: no oper ation. w ords: 1 cycles: 1 example: nop
1998 microchip technology inc. preliminary ds40191a -page 45 pic16cr54c option load option register syntax: [ label ] option oper ands: none oper ation: ( w ) ? option status aff ected: none encoding: 0000 0000 0010 descr iption: the content of the w register is loaded into the option register . w ords: 1 cycles: 1 example option b ef ore instr uction w = 0x07 after instr uction option = 0x0 7 retl w return with li teral in w syntax: [ label ] retl w k oper ands: 0 k 255 oper ation: k ? ( w ); t os ? pc status aff ected: none encoding: 1000 kkkk kkkk descr iption: the w register is loaded with the eight bit liter al 'k'. the prog r am counter is loaded from the top of the stac k (the retur n address). this is a tw o cycle instr uction. w ords: 1 cycles: 2 example : table call table ; w contains ; t able offset ;v alue . ? ;w now has table ? ;value. addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; retlw kn ; end of table b ef ore instr uction w = 0x07 after instr uction w = v alue of k 8 rlf rotate left f thr ough carr y syntax: [ label ] rlf f ,d oper ands: 0 f 31 d ? [0,1] oper ation: see descr iption belo w status aff ected: c encoding: 0011 01df ffff descr iption: the contents of register 'f' are rotated one bit to the left through the carr y flag. if 'd' is 0 the result is placed in the w register . if 'd' is 1 the result is stored bac k in register 'f'. w ords: 1 cycles: 1 example: rlf reg1,0 b ef ore instr uction reg1 = 1110 0110 c = 0 after instr uction reg1 = 1110 0110 w = 1100 1100 c = 1 rrf rotate right f thr ough carr y syntax: [ label ] rrf f ,d oper ands: 0 f 31 d ? [0,1] oper ation: see descr iption belo w status aff ected: c encoding: 0011 00df ffff descr iption: the contents of register 'f' are rotated one bit to the r ight through the carr y flag. if 'd' is 0 the result is placed in the w register . if 'd' is 1 the result is placed bac k in register 'f'. w ords: 1 cycles: 1 example: rrf reg1,0 b ef ore instr uction reg1 = 1110 0110 c = 0 after instr uction reg1 = 1110 0110 w = 0111 0011 c = 0 c register ' f ' c register ' f '
pic16cr54c ds40191a -page 46 preliminary 1998 microchip technology inc. sleep enter sleep mode syntax: [ label ] sleep oper ands: none oper ation: 00h ? wdt ; 0 ? wdt prescaler ; 1 ? t o ; 0 ? pd status aff ected: t o , pd encoding: 0000 0000 0011 descr iption: time-out status bit ( t o ) is set. the po w er do wn status bit ( pd ) is cleared. the wdt and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. see sec- tion on sleep f or more details . w ords: 1 cycles: 1 example: sleep subwf subtract w fr om f syntax: [ label ] subwf f ,d oper ands: 0 f 31 d ? [0,1] oper ation: ( f ) ?( w) ? ( dest) status aff ected: c , dc , z encoding: 0000 10df ffff descr iption: subtr act (2 s complement method ) the w register from register 'f'. if 'd' is 0 the result is stored in the w register . if 'd' is 1 the result is stored bac k in register 'f'. w ords: 1 cycles: 1 example 1 : subwf reg1, 1 bef ore instr uction reg1 = 3 w = 2 c = ? after instr uction reg1 = 1 w = 2 c = 1 ; result is positiv e e xample 2 : bef ore instr uction reg1 = 2 w = 2 c = ? after instr uction reg1 = 0 w = 2 c = 1 ; result is z ero e xample 3 : bef ore instr uction reg1 = 1 w = 2 c = ? after instr uction reg1 = ff w = 2 c = 0 ; result is negativ e
1998 microchip technology inc. preliminary ds40191a -page 47 pic16cr54c sw apf swap nibb les in f syntax: [ label ] sw apf f ,d oper ands: 0 f 31 d ? [0,1] oper ation: ( f< 3:0>) ? ( d est < 7:4>); ( f< 7:4>) ? ( d est < 3:0>) status aff ected: none encoding: 0011 10df ffff descr iption: the upper and lo w er nib b les of register 'f' are e xchanged. if 'd' is 0 the result is placed in w register . if 'd' is 1 the result is placed in register 'f'. w ords: 1 cycles: 1 example swapf reg1, 0 bef ore instr uction reg 1 = 0x a5 after instr uction reg 1 = 0x a5 w = 0x5a tris load tris register syntax: [ label ] tris f oper ands: f = 5, 6 or 7 oper ation: ( w ) ? tris register f status aff ected: none encoding: 0000 0000 0fff descr iption: tris register 'f' (f = 5, 6, or 7) is loaded with the contents of the w register w ords: 1 cycles: 1 example tris porta bef ore instr uction w = 0xa5 after instr uction trisa = 0xa5 xorl w exc lusive or li teral with w syntax: [ label ] xorl w k oper ands: 0 k 255 oper ation: (w) .xor. k ? ( w) status aff ected: z encoding: 1111 kkkk kkkk descr iption: the contents of the w register are xor?d with the eight bit liter al 'k'. the result is placed in the w register . w ords: 1 cycles: 1 example: xorlw 0xaf b ef ore instr uction w = 0xb5 after instr uction w = 0x1a xor wf exc lusive or w with f syntax: [ label ] xor wf f ,d oper ands: 0 f 31 d ? [0,1] oper ation: (w) .xor. (f) ? ( dest) status aff ected: z encoding: 0001 10df ffff descr iption: exclusiv e or the contents of the w register with register 'f'. if 'd' is 0 the result is stored in the w register . if 'd' is 1 the result is stored bac k in register 'f'. w ords: 1 cycles: 1 example xorwf reg ,1 b ef ore instr uction reg = 0xaf w = 0xb5 after instr uction reg = 0x1a w = 0xb5
pic16cr54c ds40191a -page 48 preliminary 1998 microchip technology inc. notes:
1998 microchip technology inc. preliminary ds40191a -page 49 pic16cr54c 9.0 de velopment suppor t 9.1 de velopme nt t ools the picmicr o? microcontrollers are suppor ted with a full r ange of hardw are and softw are de v elopment tools: picmaster a /picmaster ce real-time in-circuit em ulator icepic ? lo w-cost pic16c5x and pic16cxxx in-circuit em ulator pr o ma te a ii univ ersal prog r ammer picst ar t a plus entr y-le v el prototype prog r ammer picdem-1 lo w-cost demonstr ation board picdem-2 lo w-cost demonstr ation board picdem-3 lo w-cost demonstr ation board mp asm assemb ler mplab ? sim softw are sim ulator mplab-c17 (c compiler) fuzzy logic de v elopment system ( fuzzy tech a - mp) 9.2 picmaster: high p erf ormance univer sal in-cir cuit em ulator with mplab ide the picmaster univ ersal in-circuit em ulator is intended to pro vide the product de v elopment engineer with a complete microcontroller design tool set f or all microcontrollers in the pic14c000, pic12cxxx, pic16c5x, pic16cxxx and pic17cxx f amilies . picmaster is supplied with the mplab ? integ r ated de v elopment en vironment (ide), which allo ws editing, ?ak e and do wnload, and source deb ugging from a single en vironment. interchangeab le target probes allo w the system to be easily recon gured f or em ulation of diff erent processors . the univ ersal architecture of the picmaster allo ws e xpansion to suppor t all ne w microchip microcontrollers . the picmaster em ulator system has been designed as a real-time em ulation system with adv anced f eatures that are gener ally f ound on more e xpensiv e de v elopment tools . the pc compatib le 386 (and higher) machine platf or m and microsoft win do ws a 3.x en vironment w ere chosen to best mak e these f eatures a v ailab le to y ou, the end user . a ce compliant v ersion of picmaster is a v ailab le f or european union (eu) countr ies . 9.3 icepic: lo w-cost picmicr o in-cir cuit em ulator icepic is a lo w-cost in-circuit em ulator solution f or the microchip pic12cxxx, pic16c5x and pic16cxxx f amilies of 8-bit o tp microcontrollers . icepic is designed to oper ate on pc-compatib le machines r anging from 286-a t a through p entium ? based machines under windo ws 3.x en vironment. icepic f eatures real time , non-intr usiv e em ulation. 9.4 pr o ma te ii: univer sal pr ogrammer the pr o ma te ii univ ersal prog r ammer is a full-f eatured prog r ammer capab le of oper ating in stand-alone mode as w ell as pc-hosted mode . pr o ma te ii is ce compliant. the pr o ma te ii has prog r ammab le v dd and v pp supplies which allo ws it to v er ify prog r ammed memor y at v dd min and v dd max f or maxim um reliability . it has an lcd displa y f or displa ying error messages , k e ys to enter commands and a modular detachab le soc k et assemb ly to suppor t v ar ious pac kage types . in stand- alone mode the pr o ma te ii can read, v er ify or prog r am pic12cxxx, pic14c000, pic16c5x, pic16cxxx and pic17cxx de vices . it can also set con gur ation and code-protect bits in this mode . 9.5 picst ar t plus entr y le vel de velopment system the picst ar t prog r ammer is an easy-to-use , lo w-cost prototype prog r ammer . it connects to the pc via one of the com (rs-232) por ts . mplab integ r ated de v elopment en vironment softw are mak es using the prog r ammer simple and ef cient. picst ar t plus is not recommended f or production prog r amming. picst ar t plus suppor ts all pic12cxxx, pic14c000, pic16c5x, pic16cxxx and pic17cxx de vices with up to 40 pins . larger pin count de vices such as the pic16c923, pic16c924 and pic17c756 ma y be suppor ted with an adapter soc k et. picst ar t plus is ce compliant. 9.6 picdem-1 lo w-cost picmicr o demonstration boar d the picdem-1 is a simple board which demonstr ates the capabilities of se v er al of microchip s microcontrollers . the microcontrollers suppor ted are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessar y hardw are and softw are is included to r un basic demo prog r ams . the users can prog r am the sample micro controllers pro vided with the picdem-1 board, on a pr o ma te ii or picst ar t -plus prog r ammer , and easily test r mw are . the user can also connect the picdem-1 board to the picmaster em ulator and do wn load the r mw are to the em ulator f or testing.
pic16cr54c ds40191a -page 50 preliminary 1998 microchip technology inc. additional prototype area is a v ailab le f or the user to b uild some additional hardw are and connect it to the microcontroller soc k et(s). some of the f eatures include an rs-232 interf ace , a potentiometer f or sim ulated analog input, push-b utton s witches and eight leds connected to por tb . 9.7 picdem-2 lo w-cost pic16cxx demonstration boar d the picdem-2 is a simple demonstr ation board that suppor ts the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcon trollers . all the necessar y hardw are and softw are is included to r un the basic demonstr ation prog r ams . the user can prog r am the sample microcontrollers pro vided with the picdem-2 board, on a pr o ma te ii prog r ammer or picst ar t -plus , and easily test r mw are . the picmaster em ulator ma y also be used with the picdem-2 board to test r mw are . additional prototype area has been pro vided to the user f or adding additional hardw are and connecting it to the microcontroller soc k et(s). some of the f eatures include a rs-232 interf ace , push-b utton s witches , a potentiometer f or sim ulated analog input, a ser ial eepr om to demonstr ate usage of the i 2 c b us and separ ate headers f or connection to an lcd module and a k e ypad. 9.8 picdem-3 lo w-cost pic16cxxx demonstration boar d the picdem-3 is a simple demonstr ation board that suppor ts the pic16c923 and pic16c924 in the plcc pac kage . it will also suppor t future 44-pin plcc microcontrollers with a lcd module . all the necessar y hardw are and softw are is included to r un the basic demonstr ation prog r ams . the user can prog r am the sample microcontrollers pro vided with the picdem-3 board, on a pr o ma te ii prog r ammer or picst ar t plus with an adapter soc k et, and easily test r mw are . the picmaster em ulator ma y also be used with the picdem-3 board to test r mw are . additional prototype area has been pro vided to the user f or adding hardw are and connecting it to the microcontroller soc k et(s). some of the f eatures include an rs-232 interf ace , push-b utton s witches , a potentiometer f or sim ulated analog input, a ther mistor and separ ate headers f or connection to an e xter nal lcd module and a k e ypad. also pro vided on the picdem-3 board is an lcd panel, with 4 commons and 12 segments , that is capab le of displa ying time , temper ature and da y of the w eek. the picdem-3 pro vides an additional rs-232 interf ace and windo ws 3.1 softw are f or sho wing the dem ultiple x ed lcd signals on a pc . a simple ser ial interf ace allo ws the user to constr uct a hardw are dem ultiple x er f or the lcd signals . 9.9 mplab integrated de velopment en vir onment software the mplab ide softw are br ings an ease of softw are de v elopment pre viously unseen in the 8-bit microcontroller mar k et. mplab is a windo ws based application which contains: a full f eatured editor three oper ating modes - editor - em ulator - sim ulator a project manager customizab le tool bar and k e y mapping a status bar with project inf or mation extensiv e on-line help mplab allo ws y ou to: edit y our source les (either assemb ly or ?? one touch assemb le (or compile) and do wnload to picmicro tools (automatically updates all project inf or mation) deb ug using: - source les - absolute listing le t r ansf er data dynamically via dde (soon to be replaced b y ole) run up to f our em ulators on the same pc the ability to use mplab with microchip s sim ulator allo ws a consistent platf or m and the ability to easily s witch from the lo w cost sim ulator to the full f eatured em ulator with minimal retr aining due to de v elopment tools . 9.10 assemb ler (mp asm) the mp asm univ ersal macro assemb ler is a pc-hosted symbolic assemb ler . it suppor ts all microcontroller ser ies including the pic12c5xx, pic14000, pic16c5x, pic16cxxx, and pic17cxx f amilies . mp asm off ers full f eatured macro capabilities , conditional assemb ly , and se v er al source and listing f or mats . it gener ates v ar ious object code f or mats to suppor t microchip's de v elopment tools as w ell as third par ty prog r ammers . mp asm allo ws full symbolic deb ugging from picmaster, microchip s univ ersal em ulator system. mp asm has the f ollo wing f eatures to assist in de v eloping softw are f or speci c use applications . pro vides tr anslation of assemb ler source code to object code f or all microchip microcontrollers . macro assemb ly capability . produces all the les (object, listing, symbol, and special) required f or symbolic deb ug with microchip s em ulator systems . suppor ts he x (def ault), decimal and octal source and listing f or mats .
1998 microchip technology inc. preliminary ds40191a -page 51 pic16cr54c mp asm pro vides a r ich directiv e language to suppor t prog r amming of the picmicro . directiv es are helpful in making the de v elopment of y our assemb le source code shor ter and more maintainab le . 9.11 software sim ulator (mplab-sim) the mplab-sim softw are sim ulator allo ws code de v elopment in a pc host en vironment. it allo ws the user to sim ulate the picmicro ser ies microcontrollers on an instr uction le v el. on an y giv en instr uction, the user ma y e xamine or modify an y of the data areas or pro vide e xter nal stim ulus to an y of the pins . the input/output r adix can be set b y the user and the e x ecution can be perf or med in; single step , e x ecute until break, or in a tr ace mode . mplab-sim fully suppor ts symbolic deb ugging using mplab-c and mp asm. the softw are sim ulator off ers the lo w cost e xibility to de v elop and deb ug code outside of the labor ator y en vironment making it an e xcellent m ulti-project softw are de v elopment tool. 9.12 c compiler ( mplab-c17) the mplab-c code de v elopment system is a complete ? compiler and integ r ated de v elopment en vironment f or microchip s pic17cxxx f amily of microcontrollers . the compiler pro vides po w erful integ r ation capabilities and ease of use not f ound with other compilers . f or easier source le v el deb ugging, the compiler pro vides symbol inf or mation that is compatib le with the mplab ide memor y displa y . 9.13 fuzzy logic de velopment system ( fuzzy tech-mp) fuzzy tech-mp fuzzy logic de v elopment tool is a v ailab le in tw o v ersions - a lo w cost introductor y v ersion, mp explorer , f or designers to gain a comprehensiv e w or king kno wledge of fuzzy logic system design; and a full-f eatured v ersion, fuzzy tech-mp , edition f or implementing more comple x systems . both v ersions include microchip s fuzzy lab ? demonstr ation board f or hands-on e xper ience with fuzzy logic systems implementation. 9.14 mp-drivew a y ? ?application code generator mp-dr iv ew a y is an easy-to-use windo ws-based application code gener ator . with mp-dr iv ew a y y ou can visually con gure all the per ipher als in a picmicro de vice and, with a clic k of the mouse , gener ate all the initialization and man y functional code modules in c language . the output is fully compatib le with microchip s mplab-c c compiler . the code produced is highly modular and allo ws easy integ r ation of y our o wn code . mp-dr iv ew a y is intelligent enough to maintain y our code through subsequent code gener ation. 9.15 seev al a ev aluation and pr ogramming system the seev al seepr om designer s kit suppor ts all microchip 2-wire and 3-wire ser ial eepr oms . the kit includes e v er ything necessar y to read, wr ite , er ase or prog r am special f eatures of an y microchip seepr om product including smar t ser ials ? and secure ser ials . the t otal endur ance ? disk is included to aid in tr ade-off analysis and reliability calculations . the total kit can signi cantly reduce time-to-mar k et and result in an optimiz ed system. 9.16 k ee l oq a ev aluation and pr ogramming t ools k ee l oq e v aluation and prog r amming tools suppor t microchips hcs secure data products . the hcs e v aluation kit includes an lcd displa y to sho w changing codes , a decoder to decode tr ansmissions , and a prog r amming interf ace to prog r am test tr ansmitters .
pic16cr54c ds40191a -page 52 preliminary 1998 microchip technology inc. t ab le 9-1: de velopment t ools fr om micr oc hip pic12c5xx pic14000 pic16c5x pic16cxxx pic16c6x pic16c7xx pic16c8x pic16c9xx pic17c4x pic17c75x 24cxx 25cxx 93cxx hcs200 hcs300 hcs301 emulator products picmaster a / picmaster-ce in-circuit emulator icepic ? low-cost in-circuit emulator software products mplab ? integrated development environment mplab ? c17 compiler fuzzy tech a -mp explorer/edition fuzzy logic dev. tool mp-driveway ? applications code generator total endurance ? software model programmers picstart a plus low-cost universal dev. kit pro mate a ii universal programmer keeloq a programmer demo boards seeval a designers kit picdem-1 picdem-2 picdem-3 keeloq a evaluation kit
1998 microchip technology inc. preliminary ds40191a -page 53 pic16cr54c 10.0 electrical characteristics - pic16cr54c absolute maxim um ratings ? ambient temper ature under bias ............................................................................................................ ?5 c to +125 c stor age temper ature ............................................................................................................................. ?5 c to +150 c v oltage on v dd with respect to v ss .................................................................................................................. 0 to +7.5v v oltage on mclr with respect to v ss ................................................................................................................ 0 to +14v v oltage on all other pins with respect to v ss ................................................................................. ?.6v to (v dd + 0.6v) t otal po w er dissipation (1) ............................................................................................................................... ...... 800 mw max. current out of v ss pin ............................................................................................................................... ..... 150 ma max. current into v dd pin ............................................................................................................................... ....... 100 ma max. current into an input pin (t0cki only) ...................................................................................................................... 500 m a input clamp current, i ik (v i < 0 or v i > v dd ) .................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) .............................................................................................................. 20 ma max. output current sunk b y an y i/o pin .................................................................................................................. 15 ma max. output current sourced b y an y i/o pin ............................................................................................................ 15 ma max. output current sourced b y a single i/o por t a ................................................................................................ 45 ma max. output current sourced b y a single i/o por t b ................................................................................................ 45 ma max. output current sunk b y a single i/o por t a ...................................................................................................... 45 ma max. output current sunk b y a single i/o por t b ..................................................................................................... 45 ma note 1: p o w er dissipation is calculated as f ollo ws: pdis = v dd x {i dd - ? i oh } + ? {(v dd - v oh ) x i oh } + ? ( v ol x i ol ) ? no tice: stresses abo v e those listed under "maxim um ratings" ma y cause per manent damage to the de vice . this is a stress r ating only and functional oper ation of the de vice at those or an y other conditions abo v e those indicated in the oper ation listings of this speci cation is not implied. exposure to maxim um r ating conditions f or e xtended per iods ma y aff ect de vice reliability .
pic16cr54c ds40191a -page 54 preliminary 1998 microchip technology inc. 10.1 dc characteristics: pic16cr54c-04, 20 (commer cial) pic16cr54c-04i, 20i (industrial) dc characteristics p o wer suppl y pins standar d operating conditions (unless otherwise speci ed) oper ating t emper ature 0 c t a +70 c (commercial) ?0 c t a +85 c (industr ial) characteristic sym min t yp (1) max units conditions suppl y v olta g e xt , rc and lp options hs option v dd 3.0 4.5 5.5 5.5 v v ram data retention v olta g e (2) v dr 1.5* v de vice in sleep mode v dd star t v olta g e to ensure p o wer -on reset v por v ss v see section 7.4 f or details on p o w er-on reset v dd rise rate to ensure p o wer -on reset s vdd 0.05* v/ms see section 7.4 f or details on p o w er-on reset suppl y current (3) xt and rc (4) options hs option lp option, commercial lp option, industr ial i dd 1.8 4.5 14 17 2.4 16 32 40 ma ma m a m a f osc = 4.0 mhz, v dd = 5.5v f osc = 20 mhz, v dd = 5.5v f osc = 32 khz, v dd = 3.0v , wdt disab led f osc = 32 khz, v dd = 3.0v , wdt disab led p o wer do wn current (5) commercial industr ial i pd 4.0 0.25 4.0 0.25 12 4.0 14 5.0 m a m a m a m a v dd = 3.0v , wdt enab led v dd = 3.0v , wdt disab led v dd = 3.0v , wdt enab led v dd = 3.0v , wdt disab led * these par ameters are char acter iz ed b ut not tested. note 1: data in the t ypical (? yp? column is based on char acter ization results at 25 c . this data is f or design guidance only and is not tested. 2: this is the limit to which v dd can be lo w ered in sleep mode without losing ram data. 3: the supply current is mainly a function of the oper ating v oltage and frequency . other f actors such as b us loading, oscillator type , b us r ate , inter nal code e x ecution patter n, and temper ature also ha v e an impact on the current consumption. a) the test conditions f or all i dd measurements in activ e oper ation mode are: osc1 = e xter nal square w a v e , from r ail-to-r ail; all i/o pins tr istated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enab led/disab led as speci ed. b) f or standb y current measurements , the conditions are the same , e xcept that the de vice is in sleep mode . 4: does not include current through re xt. the current through the resistor can be estimated b y the f or m ula: i r = v dd /2re xt (ma) with re xt in k w . 5: the po w er do wn current in sleep mode does not depend on the oscillator type . p o w er do wn current is measured with the par t in sleep mode , with all i/o pins in hi-impedance state and tied to v dd and v ss .
1998 microchip technology inc. preliminary ds40191a -page 55 pic16cr54c 10.2 dc characteristics: pic16cr54c-04, 20, pic16cr54c-04i, 20i (commer cial, industrial) dc characteristics all pins except p o wer suppl y pins standar d operating conditions (unless otherwise speci ed) oper ating t emper ature 0 c t a +70 c (commercial) ?0 c t a +85 c (industr ial) oper ating v oltage v dd r ange is descr ibed in section 10.1 characteristic sym min t yp (1) max units conditions input lo w v olta g e i/o p or ts i/o p or ts mclr (schmitt t r igger) t0cki (schmitt t r igger) osc1 (schmitt t r igger) osc1 v il v ss v ss v ss v ss v ss 0.8 v dd 0.15 v dd 0.15 v dd 0.15 v dd 0.15 v dd 0.3 v dd v v v v v pin at hi-impedance 4.5v , vdd 5.5v pin at hi-impedance 2.5v , vdd 4.5v rc option only (4) xt , hs and lp options input high v olta g e i/o por ts mclr (schmitt t r igger) t0cki (schmitt t r igger) osc1 (schmitt t r igger) osc1 v ih 0.25 v dd +0.8v 2.0 0.85 v dd 0.85 v dd 0.85 v dd 0.7 v dd v dd v dd v dd v dd v dd v dd v v v v v v f or all v dd (5) 4.5v < v dd 5.5v (5) rc option only (4) xt , hs and lp options hysteresis of sc hmitt t rig g er inputs v hys 0.15v dd * v input leaka g e current (3) i/o por ts mclr t0cki osc1 i il -1.0 -5.0 -3.0 -3.0 0.5 0.5 0.5 0.5 +1.0 +5.0 +3.0 +3.0 m a m a m a m a m a for v dd 5.5v v ss v pin v dd , pin at hi-impedance v pin = v ss +0.25v (2) v pin = v dd (2) v ss v pin v dd v ss v pin v dd , xt , hs and lp options output lo w v olta g e i/o por ts osc2/clk out v ol 0.6 0.6 v v i o l = 5.0 ma, v dd = 4.5v i o l = 1.6 ma, v dd = 4.5v , rc option only output high v olta g e i/o por ts (3) osc2/clk out v oh v dd -0.7 v dd -0.7 v v i o h = -3.0 ma, v dd = 4.5v i o h = -1.0 ma, v dd = 4.5v , rc option only * these par ameters are char acter iz ed b ut not tested. note 1: data in the t ypical (? yp? column is based on char acter ization results at 25 c . this data is f or design guidance only and is not tested. 2: the leakage current on the mclr / v pp pin is strongly dependent on the applied v oltage le v el. the speci ed le v- els represent nor mal oper ating conditions . higher leakage current ma y be measured at diff erent input v oltage . 3: negativ e current is de ned as coming out of the pin. 4: f or the rc option, the osc1/clkin pin is a schmitt t r igger input. it is not recommended that the pic16cr54c be dr iv en with e xter nal cloc k in rc mode . 5: the user ma y use the better of the tw o speci cations .
pic16cr54c ds40191a -page 56 preliminary 1998 microchip technology inc. 10.3 timing p arameter symbology and load conditions the timing par ameter symbols ha v e been created f ollo wing one of the f ollo wing f or mats: 1. tpps2pps 2. tpps t f f requency t time lo w ercase subscr ipts (pp) and their meanings: pp 2 to mc mclr c k clk out osc oscillator cy cycle time os osc1 dr t de vice reset timer t0 t0cki io i/o por t wdt w atchdog timer uppercase letters and their meanings: s f f all p p er iod h high r rise i in v alid (hi-impedance) v v alid l lo w z hi-impedance figure 10-1: load conditions - pic16cr54c c l v ss pin c l = 50 pf f or all pins e xcept osc2 15 pf f or osc2 in xt , hs or lp options when e xter nal cloc k is used to dr iv e osc1
1998 microchip technology inc. preliminary ds40191a -page 57 pic16cr54c 10.4 timing dia grams and speci cations figure 10-2: external cloc k timing - pic16cr54c t ab le 10-1: external cloc k timing requirements - pic16cr54c a c characteristics standar d operating conditions (unless otherwise speci ed) oper ating t emper ature 0 c t a +70 c (commercial) ?0 c t a +85 c (industr ial) oper ating v oltage v dd r ange is descr ibed in section 10.1 p arameter no. sym characteristic min t yp (1) max units conditions f osc exter nal clkin f requency (2) dc 4.0 mhz xt osc mode dc 4.0 mhz hs osc mode (04) dc 20 mhz hs osc mode (20) dc 200 khz lp osc mode oscillator f requency (2) dc 4.0 mhz rc osc mode 0.455 4.0 mhz xt osc mode 4 4.0 mhz hs osc mode (04) 4 20 mhz hs osc mode (20) 5 200 khz lp osc mode 1 t osc exter nal clkin p er iod (2) 250 ns xt osc mode 250 ns hs osc mode (04) 50 ns hs osc mode (20) 5.0 m s lp osc mode oscillator p er iod (2) 250 ns rc osc mode 250 2,200 ns xt osc mode 250 250 ns hs osc mode (04) 50 250 ns hs osc mode (20) 5.0 200 m s lp osc mode * these par ameters are char acter iz ed b ut not tested. note 1: data in the t ypical (? yp? column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. 2: all speci ed v alues are based on char acter ization data f or that par ticular oscillator type under standard oper ating condi- tions with the de vice e x ecuting code . exceeding these speci ed limits ma y result in an unstab le oscillator oper ation and/or higher than e xpected current consumption. when an e xter nal cloc k input is used, the ?ax cycle time limit is ?c (no cloc k) f or all de vices . 3: instr uction cycle per iod ( t cy ) equals f our times the input oscillator time base per iod. osc1 clk out q4 q1 q2 q3 q4 q1 1 3 3 4 4 2
pic16cr54c ds40191a -page 58 preliminary 1998 microchip technology inc. 2 t cy instr uction cycle time (3) 4/f osc 3 t osl, t osh cloc k in (osc1) lo w or high time 50* ns xt oscillator 20* ns hs oscillator 2.0* m s lp oscillator 4 t osr, t osf cloc k in (osc1) rise or f all time 25* ns xt oscillator 25* ns hs oscillator 50* ns lp oscillator t ab le 10-1: external cloc k timing requirements - pic16cr54c (contin ued) a c characteristics standar d operating conditions (unless otherwise speci ed) oper ating t emper ature 0 c t a +70 c (commercial) ?0 c t a +85 c (industr ial) oper ating v oltage v dd r ange is descr ibed in section 10.1 p arameter no. sym characteristic min t yp (1) max units conditions * these par ameters are char acter iz ed b ut not tested. note 1: data in the t ypical (? yp? column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. 2: all speci ed v alues are based on char acter ization data f or that par ticular oscillator type under standard oper ating condi- tions with the de vice e x ecuting code . exceeding these speci ed limits ma y result in an unstab le oscillator oper ation and/or higher than e xpected current consumption. when an e xter nal cloc k input is used, the ?ax cycle time limit is ?c (no cloc k) f or all de vices . 3: instr uction cycle per iod ( t cy ) equals f our times the input oscillator time base per iod.
1998 microchip technology inc. preliminary ds40191a -page 59 pic16cr54c figure 10-3: clk out and i/o timing - pic16cr54c t ab le 10-2: clk out and i/o timing requirements - pic16cr54c a c characteristics standar d operating conditions (unless otherwise speci ed) oper ating t emper ature 0 c t a +70 c (commercial) ?0 c t a +85 c (industr ial) oper ating v oltage v dd r ange is descr ibed in section 10.1 p arameter no. sym characteristic min t yp (1) max units 10 t osh2c kl osc1 - to clk out (2) 15 30** ns 11 t osh2c kh osc1 - to clk out - (2) 15 30** ns 12 tc kr clk ou t r ise time (2) 5.0 15** ns 13 tc kf clk out f all time (2) 5.0 15** ns 14 tc kl2iov clk out to p or t out v alid (2) 40** ns 15 tiov2c kh p or t in v alid bef ore clk out - (2) 0.25 t cy + 30* ns 16 tc kh2ioi p or t in hold after clk out - (2) 0* ns 17 t osh2iov osc1 - (q1 cycle) to p or t out v alid (3) 100* ns 18 t osh2ioi osc1 - (q2 cycle) to p or t input in v alid (i/o in hold time) tbd ns 19 tiov2osh p or t input v alid to osc1 - (i/o in setup time) tbd ns 20 tior p or t output r ise time (3) 10 25** ns 21 tiof p or t output f all time (3) 10 25** ns * these par ameters are char acter iz ed b ut not tested. ** these par ameters are design targets and are not tested. no char acter ization data a v ailab le at this time . note 1: data in the t ypical (? yp? column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. 2: measurements are tak en in rc mode where clk out output is 4 x t osc . 3: see figure 10-1 f or loading conditions . osc1 clk out i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 18 15 11 12 16 old v alue ne w v alue note: all tests m ust be done with speci ed capacitiv e loads (see data sheet) 50 pf on i/o pins and clk out . 19
pic16cr54c ds40191a -page 60 preliminary 1998 microchip technology inc. figure 10-4: reset, w atc hdog timer , and de vice reset timer timing - pic16cr54c t ab le 10-3: reset, w atc hdog timer , and de vice reset timer - pic16cr54c a c characteristics standar d operating conditions (unless otherwise speci ed) oper ating t emper ature 0 c t a +70 c (commercial) ?0 c t a +85 c (industr ial) oper ating v oltage v dd r ange is descr ibed in section 10.1 p arameter no. sym characteristic min t yp (1) max units conditions 30 tmcl mclr pulse width (lo w) 1000* ns v dd = 5.0v 31 t wdt w atchdog timer time-out p er iod (no prescaler) 9.0* 18* 30* ms v dd = 5.0v (commercial) 32 t drt de vice reset timer p er iod 9.0* 18* 30* ms v dd = 5.0v (commercial) 34 t io z i/o hi-impedance from mclr lo w 100* 300* 1000* ns * these par ameters are char acter iz ed b ut not tested. note 1: data in the t ypical (? yp? column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. v dd mclr inter nal por dr t time-out inter nal reset w atchdog timer reset 32 31 34 i/o pin 32 32 34 (note 1) note 1: i/o pins m ust be tak en out of hi-impedance mode b y enab ling the output dr iv ers in softw are . 30
1998 microchip technology inc. preliminary ds40191a -page 61 pic16cr54c figure 10-5: timer0 cloc k timings - pic16cr54c t ab le 10-4: timer0 cloc k requirements - pic16cr54c a c characteristics standar d operating conditions (unless otherwise speci ed) oper ating t emper ature 0 c t a +70 c (commercial) ?0 c t a +85 c (industr ial) oper ating v oltage v dd r ange is descr ibed in section 10.1 p arameter no. sym characteristic min t yp (1) max units conditions 40 tt0h t0cki high pulse width - no prescaler 0.5 t cy + 20* ns - with prescaler 10* ns 41 tt0l t0cki lo w pulse width - no prescaler 0.5 t cy + 20* ns - with prescaler 10* ns 42 tt0p t0cki p er iod 20 or t cy + 40 * n ns whiche v er is g reater . n = prescale v alue (1, 2, 4,..., 256) * these par ameters are char acter iz ed b ut not tested. note 1: data in the t ypical (? yp? column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. t0cki 40 41 42
pic16cr54c ds40191a -page 62 preliminary 1998 microchip technology inc. notes:
1998 microchip technology inc. preliminary ds40191a -page 63 pic16cr54c pic16cr54c 11.0 dc and a c characteristics - pic16cr54c the g r aphs and tab les pro vided in this section are f or design guidance and are not tested or guar anteed. i n some g r aphs or tab les the data presented are outside speci ed oper ating r ange (e .g., outside speci ed v dd r ange). this is f or inf or mation only and de vices will o per ate proper ly only within the speci ed r ange . the data presented in this section is a statistical summar y of data collected on units from diff erent lots o v er a per iod of time . t ypical represents the mean of the distr ib ution while ?ax or ?in represents (mean + 3 s ) and (mean ?3 s ) respectiv ely , where s is standard de viation. figure 11-1: t ypical rc oscillator frequenc y vs . t emperature t ab le 11-1: rc oscillator frequencies ce xt re xt a vera g e fosc @ 5 v , 25 c 20 pf 3.3 k 4.973 m hz 27% 5 k 3.82 m hz 21% 10 k 2.22 m hz 21% 100 k 262.15 k hz 31% 100 pf 3.3 k 1.63 m hz 13% 5 k 1.19 mhz 13% 10 k 684.64 khz 18% 100 k 71.56 khz 25% 300 pf 3.3 k 660 k hz 10% 5. 0 k 484.1 khz 14% 10 k 267.63 khz 15% 160 k 29.44 khz 19% the frequencies are measured on dip pac kages . the percentage v ar iation indicated here is par t -t o -p ar t v ar iation due to nor mal process distr ib ution. t he v ar iation i ndicated is 3 standard de viation from a v er age v alue f or v dd = 5 v . f osc f osc (25 c) 1.10 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 0 10 20 25 30 40 50 60 70 t( c) f requency nor maliz ed to +25 c v dd = 5.5 v v dd = 3.5 v re xt 3 10 k w ce xt = 100 pf 0.88
pic16cr54c pic16cr54c ds40191a -page 64 preliminary 1998 microchip technology inc. figure 11-2: t ypical rc oscillator frequenc y vs . v dd , c ext = 20 p f figure 11-3: t ypical rc oscillator frequenc y vs . v dd , c ext = 100 p f 0.00 1.00 2.00 3.00 4.00 5.00 6.00 2.5 3 3.5 4 4.5 5 5.5 6 vdd(volts) fosc(mhz) r=3.3k r=5.0k r=10k r=100k cext=20pf, t=25c 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.5 3 3.5 4 4.5 5 5.5 6 vdd(volts) fosc(mhz) r=3.3k r=5.0k r=10k r=100k cext=100pf, t=25c
1998 microchip technology inc. preliminary ds40191a -page 65 pic16cr54c pic16cr54c figure 11-4: t ypical rc oscillator frequenc y vs . v dd , c ext = 300 p f figure 11-5: t ypical i pd vs . v dd , w atc hdog disab led (25 c) 0.00 100.00 200.00 300.00 400.00 500.00 600.00 700.00 2.5 3 3.5 4 4.5 5 5.5 6 vdd(volts) fosc(khz) r=3.3k r=5.0k r=10k r=100k cext=300pf, t=25c 0 0.5 1 1.5 2 2.5 2.5 3 3.5 4 4.5 5 5.5 6 vdd(volts) ipd(na) i pd ( m a)
pic16cr54c pic16cr54c ds40191a -page 66 preliminary 1998 microchip technology inc. figure 11-6: t ypical i pd vs . v dd , w atc hdog enab led (25 c) figure 11-7: t ypical i pd vs . v dd , w atc hdog enab led ( 40 c, 85 c) vd d (v olts ) ipd ( u a) 25 20 15 5 0 2.5 3 3.5 4.5 5.5 4 5 6 10 vd d (v olts ) ipd ( u a) 35 25 15 5 0 2.5 3 3.5 4.5 5.5 4 5 6 10 30 20 (-40 c) (+85 c)
1998 microchip technology inc. preliminary ds40191a -page 67 pic16cr54c pic16cr54c figure 11-8: v th (input threshold t rip p oint v olta g e) of i/o pins vs . v dd figure 11-9: v ih , v il of mclr , t0cki and osc1 (in rc mode) vs . v dd 2.00 1.80 1.60 1.40 1.20 1.00 2.5 3.0 3.5 4.0 4.5 5.0 v dd (v olts) 0.80 0.60 5.5 6.0 t yp ( + 25 c) v th (v olts) 3.5 3.0 2.5 2.0 1.5 1.0 2.5 3.0 3.5 4.0 4.5 5.0 v dd (v olts) 0.5 0.0 5.5 6.0 v ih , v il (v olts) 4.0 4.5 v ih m in ( ? 0 c to + 85 c) v ih m ax ( ? 0 c to + 85 c) v ih t yp + 25 c v il m in ( ? 0 c to + 85 c) v il m ax ( ? 0 c to + 85 c) v il t yp + 25 c note: these input pins ha v e schmitt t r igger input b uff ers .
pic16cr54c pic16cr54c ds40191a -page 68 preliminary 1998 microchip technology inc. figure 11-10: v th (input threshold t rip p oint v olta g e) of osc1 input (in xt , hs, and lp modes) vs . v dd figure 11-11: t ypical i dd vs. frequenc y ( wdt dis, rc mode @ 20 p f , 2 5 c ) 2.4 2.2 2.0 1.8 1.6 1.4 2.5 3.0 3.5 4.0 4.5 5.0 v dd (v olts) 1.2 1.0 5.5 6.0 t yp ( + 25 c) v th (v olts) 2.6 2.8 3.0 3.2 3.4 10 100 1000 10000 100000 1000000 10000000 freq(hz) idd(ua) 2.5v 3.5v 4.5v 5.5v
1998 microchip technology inc. preliminary ds40191a -page 69 pic16cr54c pic16cr54c figure 11-12: t ypical i dd vs. frequenc y (wdt dis, rc mode @ 100 p f , 25 c) figure 11-13: t ypical i dd vs. frequenc y (wdt dis, rc mode @ 300 p f , 25 c) 10 100 1000 10000 10000 100000 1000000 10000000 freq(hz) idd(ua) 2.5v 3.5v 4.5v 5.5v 10 100 1000 10000 10000 100000 1000000 freq(hz) idd(ua) 2.5v 3.5v 4.5v 5.5v
pic16cr54c pic16cr54c ds40191a -page 70 preliminary 1998 microchip technology inc. figure 11-14: wdt timer time-out p eriod vs . v dd 50 45 40 35 30 25 20 15 10 5 2 3 4 5 6 7 v dd (v olts) wdt per iod (ms) t yp +125 c t yp +85 c t yp + 25 c t yp ?0 c
1998 microchip technology inc. preliminary ds40191a -page 71 pic16cr54c pic16cr54c figure 11-15: i oh vs. v oh , v dd = 3 v figure 11-16: i oh vs. v oh , v dd = 5 v 0 ? ? 0 ? 5 ? 0 ? 5 0 0.5 1.0 1.5 2.0 2.5 v oh (v olts) i oh ( ma) min +85 c 3.0 t yp + 25 c max ? 0 c 0 ? 0 ? 0 ? 0 ? 0 1.5 2.0 2.5 3.0 3.5 4.0 v oh (v olts) i oh ( ma) t yp ? 0 c 4.5 5.0 t yp +8 5 c t yp +12 5 c t yp +25 c figure 11-17: i ol vs. v ol , v dd = 3 v figure 11-18: i ol vs. v ol , v dd = 5 v 45 40 35 30 25 20 15 10 5 0 0 .0 0.5 1.0 1.5 2.0 2.5 v ol (v olts) i ol ( ma) min +85 c max ? 0 c t yp + 25 c 3.0 90 80 70 60 50 40 30 20 10 0 0 .0 0.5 1.0 1.5 2.0 2.5 v ol (v olts) i ol ( ma) min + 85 c max ? 0 c t yp + 25 c 3.0
pic16cr54c pic16cr54c ds40191a -page 72 preliminary 1998 microchip technology inc. notes:
1998 microchip technology inc. preliminary ds40191a -page 73 pic16cr54c 12.0 p ac ka ging inf ormation 12.1 p ac ka g e marking inf ormation mmmmmmmmmmmm xxx mmmmmmmm xxxxxxx aabb cde 18-lead pdip pic16cr54c- 04/p123 9813 hba example leg end: mm...m microchip par t n umber inf or mation xx...x customer speci c inf or mation* aa y ear code (last 2 digits of calendar y ear) bb w eek code (w eek of j an uar y 1 is w eek ?1? c f acility code of the plant at which w af er is man uf actured o = outside v endor c = 5 line s = 6 line h = 8 line d mask re vision n umber e assemb ly code of the plant or countr y of or igin in which par t w as assemb led * standard r om mar king consists of microchip par t n umber , y ear code , w eek code , f acility code , mask re v#, and assemb ly code . f or r om mar king be y ond this , cer tain pr ice adders apply . please chec k with y our microchip sales of ce . note : in the e v ent the full microchip par t n umber cannot be mar k ed on one line , it will be carr ied o v er to the ne xt line thus limiting the n umber of a v ailab le char acters f or customer speci c inf or mation. 18-lead soic mmmmmmmmm aabb cde xxxxxxxxx 20-lead ssop xxxxxxx x aabb cde mmmmmmmm example pic16cr54c- 9810 hdk 04i/s0218 example 04i/218 9810 hbp pic16cr54c
pic16cr54c ds40191a -page 74 preliminary 1998 microchip technology inc. p ac ka g e t ype: k04-007 18-lead plastic dual in-line (p) ?300 mil * controlling p ar ameter . ? dimension ?1 does not include dam-bar protr usions . dam-bar protr usions shall not e xceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension ?1. dimensions ? and ? do not include mold ash or protr usions . mold ash or protr usions shall not e xceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions ? or ?. units inches* millimeters dimension limits min nom max min nom max pcb ro w spacing 0.300 7.62 number of pins n 18 18 pitch p 0.100 2.54 lo w er lead width b 0.013 0.018 0.023 0.33 0.46 0.58 upper lead width b1 ? 0.055 0.060 0.065 1.40 1.52 1.65 shoulder radius r 0.000 0.005 0.010 0.00 0.13 0.25 lead thic kness c 0.005 0.010 0.015 0.13 0.25 0.38 t op to seating plane a 0.110 0.155 0.155 2.79 3.94 3.94 t op of lead to seating plane a1 0.075 0.095 0.115 1.91 2.41 2.92 base to seating plane a2 0.000 0.020 0.020 0.00 0.51 0.51 tip to seating plane l 0.125 0.130 0.135 3.18 3.30 3.43 p ac kage length d 0.890 0.895 0.900 22.61 22.73 22.86 molded p ac kage width e 0.245 0.255 0.265 6.22 6.48 6.73 radius to radius width e1 0.230 0.250 0.270 5.84 6.35 6.86 ov er all ro w spacing eb 0.310 0.349 0.387 7.87 8.85 9.83 mold dr aft angle t op a 5 10 15 5 10 15 mold dr aft angle bottom b 5 10 15 5 10 15 r n 2 1 d e c eb b e1 a p a1 l b1 b a a2
1998 microchip technology inc. preliminary ds40191a -page 75 pic16cr54c p ac ka g e t ype: k04-051 18-lead plastic small outline (so) ? wide , 300 mil 0.014 0.009 0.010 0.011 0.005 0.005 0.010 0.394 0.292 0.450 0.004 0.048 0.093 min n number of pins mold dr aft angle bottom mold dr aft angle t op lo w er lead width chamf er distance outside dimension molded p ac kage width molded p ac kage length ov er all p ac k. height lead thic kness radius center line f oot angle f oot length gull wing radius shoulder radius standoff shoulder height b a r2 r1 e1 a2 a1 x f b ? c l1 l e d a dimension limits pitch units p 18 18 0 0 12 12 15 15 4 0.020 0 0.017 0.011 0.015 0.016 0.005 0.005 0.407 0.296 0.456 0.008 0.058 0.099 0.029 0.019 0.012 0.020 0.021 0.010 0.010 8 0.419 0.299 0.462 0.011 0.068 0.104 0 0 12 12 15 15 0.42 0.27 0.38 0.41 0.13 0.13 0.50 10.33 7.51 11.58 0.19 1.47 2.50 0.25 0 0.36 0.23 0.25 0.28 0.13 0.13 10.01 7.42 11.43 0.10 1.22 2.36 0.74 4 8 0.48 0.30 0.51 0.53 0.25 0.25 10.64 7.59 11.73 0.28 1.73 2.64 inches* 0.050 nom max 1.27 millimeters min nom max n 2 1 r2 r1 l1 l b c f x 45 d p b e e1 a a1 a2 a * controlling p ar ameter . ? dimension ? does not include dam-bar protr usions . dam-bar protr usions shall not e xceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension ? . dimensions ? and ? do not include mold ash or protr usions . mold ash or protr usions shall not e xceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions ? or ?.
pic16cr54c ds40191a -page 76 preliminary 1998 microchip technology inc. p ac ka g e t ype: k04-072 20-lead plastic shrink small outine (ss) ?5.30 mm min p pitch mold dr aft angle bottom mold dr aft angle t op lo w er lead width radius center line gull wing radius shoulder radius outside dimension molded p ac kage width molded p ac kage length shoulder height ov er all p ac k. height lead thic kness f oot angle f oot length standoff number of pins b a c f a2 a1 a n e1 b ? l1 r2 l r1 e d dimension limits units 0.65 0.026 8 0 0 5 5 10 10 0.012 0.007 0.005 0.020 0.005 0.005 0.306 0.208 0.283 0.005 0.036 0.073 20 0.301 0 0.010 0.005 0.000 0.015 0.005 0.005 0.205 0.278 0.002 0.026 0.068 0.311 0.015 0.009 0.010 0.025 0.010 0.010 4 8 0.212 0.289 0.008 0.046 0.078 0 0 5 5 10 10 7.65 0.25 0.13 0.00 0.38 0.13 0.13 0 5.20 7.07 0.05 0.66 1.73 7.90 7.78 4 0.32 0.18 0.13 0.13 0.51 0.13 0.38 0.22 0.25 0.25 0.64 0.25 5.29 7.20 0.13 20 1.86 0.91 5.38 7.33 0.21 1.99 1.17 nom inches max nom millimeters* min max n 1 2 r1 r2 d p b e1 e l1 l c b f a a1 a a2 * controlling p ar ameter . ? dimension ? does not include dam-bar protr usions . dam-bar protr usions shall not e xceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension ? . dimensions ? and ? do not include mold ash or protr usions . mold ash or protr usions shall not e xceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions ? or ?.
1998 microchip technology inc. preliminary ds40191a -page 77 pic16cr54c appendix a: compatibility t o con v er t code wr itten f or pic16cxx to pic16c 5x , the user should tak e the f ollo wing steps: 1. chec k an y call , goto or instr uctions that modify the pc to deter mine if an y prog r am memor y page select oper ations (p a2, p a1, p a0 bits) need to be made . 2. re visit an y computed jump oper ations (wr ite to pc or add to pc , etc.) to mak e sure page bits are set proper ly under the ne w scheme . 3. eliminate an y special function register page s witching. rede ne data v ar iab les to reallocate them. 4. v er ify all wr ites to st a tus , option, and fsr registers since these ha v e changed. 5. change reset v ector to proper v alue f or processor used. 6. remo v e an y use of the addlw and sublw instr uctions . 7. re wr ite an y code segments that use interr upts .
pic16cr54c ds40191a -page 78 preliminary 1998 microchip technology inc. notes:
1998 microchip technology inc. ds40191a -page 79 pic16cr54c inde x a absolute maximum ratings ............................................... 53 alu ...................................................................................... 9 applications .......................................................................... 5 architectural overview ......................................................... 9 assembler mpasm assembler ............................................................ 50 b block diagram on-chip reset circuit ........................................................ 29 pic16cr54c series block diagram .................................. 10 timer0 ................................................................................ 21 tmr0/wdt prescaler ........................................................ 24 watchdog timer ................................................................. 33 brown-out protection circuit ............................................. 34 c carry bit ............................................................................... 9 clocking scheme ............................................................... 12 code protection ........................................................... 25, 35 configuration bits ............................................................... 25 configuration word ............................................................ 25 pic16cr54c ..................................................................... 25 d dc and ac characteristics - pic16cr54c ....................... 63 dc characteristics ............................................................. 54 development support ........................................................ 49 development tools ............................................................ 49 device varieties ................................................................... 7 digit carry bit ....................................................................... 9 e electrical characteristics pic16cr54c ..................................................................... 53 external power-on reset circuit ....................................... 30 f family of devices pic16c5x ............................................................................ 6 features ............................................................................... 1 fsr .................................................................................... 29 fsr register ..................................................................... 18 fuzzy logic dev. system ( fuzzy tech -mp) ................... 51 i i/o interfacing .................................................................... 19 i/o ports ............................................................................. 19 i/o programming considerations ....................................... 20 icepic low-cost pic16cxxx in-circuit emulator ........... 49 indf ................................................................................... 29 indf register .................................................................... 18 indirect data addressing .................................................... 18 instruction cycle ................................................................ 12 instruction flow/pipelining ................................................. 12 instruction set summary .................................................... 37 k keeloq evaluation and programming tools ................... 51 l loading of pc .................................................................... 17 m mclr ................................................................................ 29 memory map ...................................................................... 13 pic16c54s/cr54s/c55s ................................................... 13 memory organization ........................................................ 13 data memory ..................................................................... 13 program memory ............................................................... 13 mp-driveway - application code generator ................. 51 mplab c ........................................................................... 51 mplab integrated development environment software ... 50 o one-time-programmable (otp) devices ............................ 7 option register .............................................................. 16 osc selection .................................................................... 25 oscillator configurations ................................................... 26 oscillator types hs ...................................................................................... 26 lp ...................................................................................... 26 rc ..................................................................................... 26 xt ...................................................................................... 26 p package marking information ............................................ 73 packaging information ....................................................... 73 pc ................................................................................ 17, 29 pic16cr54c product identification system ..................... 83 picdem-1 low-cost picmicro demo board .................... 49 picdem-2 low-cost pic16cxx demo board .................. 50 picdem-3 low-cost pic16cxxx demo board ............... 50 picmaster in-circuit emulator .................................... 49 picstart plus entry level development system ........ 49 pin configurations ................................................................ 1 pinout description - pic16cr54c .................................... 11 por device reset timer (drt) .......................................... 25, 32 pd ................................................................................ 28, 34 power-on reset (por) ......................................... 25, 29, 30 to ................................................................................ 28, 34 porta ........................................................................ 19, 29 portb ........................................................................ 19, 29 power-down mode ............................................................ 35 prescaler ........................................................................... 24 pro mate ii universal programmer ............................. 49 program counter ............................................................... 17 q q cycles ............................................................................. 12 quick-turnaround-production (qtp) devices ...................... 7 r rc oscillator ..................................................................... 27 read only memory (rom) devices ..................................... 7 read-modify-write ............................................................. 20 register file map .............................................................. 13 registers special function ................................................................ 13 reset ........................................................................... 25, 28 reset on brown-out .......................................................... 34 s seeval evaluation and programming system ............. 51 serialized quick-turnaround-production (sqtp) devices .. 7 sleep ......................................................................... 25, 35 software simulator (mplab-sim) ..................................... 51 special features of the cpu ............................................. 25
pic16cr54c ds40191a -page 80 1998 microchip technology inc. special function registers ................................................ 13 stack .................................................................................. 17 status ............................................................................. 29 status register ........................................................... 9, 15 t timer0 switching prescaler assignment ........................................ 24 timer0 (tmr0) module ...................................................... 21 tmr0 with external clock .................................................. 23 timing diagrams and specifications .................................. 57 timing parameter symbology and load conditions .......... 56 tris registers ................................................................... 19 u uv erasable devices ........................................................... 7 w w ........................................................................................ 29 wake-up from sleep ........................................................ 35 watchdog timer (wdt) ............................................... 25, 32 period ................................................................................. 32 programming considerations ............................................. 32 z zero bit ................................................................................. 9
1998 microchip technology inc. ds40191a -page 81 pic16cr54c systems inf ormation and upgrade hot line the systems inf or mation and upg r ade line pro vides system users a listing of the latest v ersions of all of microchip's de v elopment systems softw are products . plus , this line pro vides inf or mation on ho w customers can receiv e an y currently a v ailab le upg r ade kits .the hot line numbers are: 1-800-755-2345 f or u .s . and most of canada, and 1-602-786-7302 f or the rest of the w or ld. t rademarks: the microchip name , logo , pic , picst ar t , picmaster and pr o ma te are registered tr ademar ks of microchip t echnology incor por ated in the u .s .a. and other countr ies . picmicro , fle x r om, mplab and fuzzy- lab are tr ademar ks and sqtp is a ser vice mar k of micro- chip in the u .s .a. fuzzy tech is a registered tr ademar k of inf or m softw are cor por ation. ibm, ibm pc-a t are registered tr ademar ks of inter national business machines cor p . p entium is a tr ademar k of intel cor por ation. windo ws is a tr ademar k and ms-dos , microsoft windo ws are registered tr ade- mar ks of microsoft cor por ation. compuser v e is a regis- tered tr ademar k of compuser v e incor por ated. all other tr ademar ks mentioned herein are the proper ty of their respectiv e companies . on-line suppor t microchip pro vides on-line suppor t on the microchip w or ld wide w eb (www) site . the w eb site is used b y microchip as a means to mak e les and inf or mation easily a v ailab le to customers . t o vie w the site , the user m ust ha v e access to the inter net and a w eb bro wser , such as netscape or microsoft explorer . files are also a v ailab le f or ftp do wnload from our ftp site . connecting to the micr oc hip internet w eb site the microchip w eb site is a v ailab le b y using y our f a v or ite inter net bro wser to attach to: www .micr oc hip.com the le tr ansf er site is a v ailab le b y using an ftp ser- vice to connect to: ftp://ftp.futureone .com/pub/micr oc hip the w eb site and le tr ansf er site pro vide a v ar iety of ser vices . users ma y do wnload les f or the latest de v elopment t ools , data sheets , application notes , user's guides , ar ticles and sample prog r ams . a v ar i- ety of microchip speci c b usiness inf or mation is also a v ailab le , including listings of microchip sales of ces , distr ib utors and f actor y representativ es . other data a v ailab le f or consider ation is: latest microchip press releases t echnical suppor t section with f requently ask ed questions design tips de vice err ata job p ostings microchip consultant prog r am member listing links to other useful w eb sites related to microchip products conf erences f or products , de v elopment systems , technical inf or mation and more listing of seminars and e v ents 980106
pic16cr54c ds40191a -page 82 1998 microchip technology inc. reader response it is our intention to pro vide y ou with the best documentation possib le to ensure successful use of y our microchip prod- uct. if y ou wish to pro vide y our comments on organization, clar ity , subject matter , and w a ys in which our documentation can better ser v e y ou, please f ax y our comments to the t echnical pub lications manager at (602) 786-7578. please list the f ollo wing inf or mation, and use this outline to pro vide us with y our comments about this data sheet . 1. what are the best f eatures of this document? 2. ho w does this document meet y our hardw are and softw are de v elopment needs? 3. do y ou nd the organization of this data sheet easy to f ollo w? if not, wh y? 4. what additions to the data sheet do y ou think w ould enhance the str ucture and subject? 5. what deletions from the data sheet could be made without aff ecting the o v er all usefulness? 6. is there an y incorrect or misleading inf or mation (what and where)? 7. ho w w ould y ou impro v e this document? 8. ho w w ould y ou impro v e our softw are , systems , and silicon products? t o: t echnical pub lications manager re: reader response t otal p ages sent f rom: name compan y address city / state / zip / countr y t elephone: (_______) _________ - _________ application (optional): w ould y ou lik e a reply? y n de vice: liter ature number : questions: f ax: (______) _________ - _________ ds40191a pic16cr54c
1998 microchip technology inc. preliminary ds40191a -page 83 pic16cr54c pic16cr54c pr oduct identification system t o order or obtain inf or mation, e .g., on pr icing or deliv er y , ref er to the f actor y or the listed sales of ce . p ar t no . -xx x /xx xxx p attern p ac ka g e t emperature rang e frequenc y rang e de vice de vice pic16cr54c (2) , pic16cr 54c t ( 3) frequenc y rang e 04 20 c = 4 mhz = 20 mhz t emperature rang e b (1) i = 0 c to +70 c (commercial) = -40 c to +85 c (industr ial) p ac ka g e p s o s s = pdi p = soic (gull wing, 300 mil body ) = ssop (209 mil body ) p attern 3-digit p atter n code f or r om (b lank otherwise) examples: a) pic16c r54c - 0 4/p 301 = co mmercial temp ., pdip pac kage , 4mhz, nor mal v dd limitis , patter n #301 . b) pic16cr54c - 20i/p355 = r om pro- g r am memor y , industr ial temp ., pdip pac kage , 20mhz, nor mal v dd limits . note 1: b = b lank 2: cr = r om v ersion, standard v dd r ange 3: t = in tape and reel - soic , ssop pac kages only .
information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip t echnology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectua l property rights arising from such use or other wise. use of microchip s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or other wise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip t echnology inc. in the u.s.a. and other countries. all rights reser ved. all other trademarks mentioned herein are the property of their respective companies. ds40191a -page 84 ? 1998 microchip technology inc. all r ights reser v ed. ? 1998 , microchip t echnology incor por ated, usa. 4/98 pr inted on recycled paper . m americas corporate of ce microchip t echnology inc. 2355 w est chandler blvd. chandler , az 85224-6199 t el: 602-786-7200 f ax: 602-786-7277 t echnical suppor t: 602 786-7627 w eb: http://www .microchip .com atlanta microchip t echnology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 t el: 770-640-0034 f ax: 770-640-0307 boston microchip t echnology inc. 5 mount ro y al a v en ue mar lborough, ma 01752 t el: 508-480-9990 f ax: 508-480-8575 chica go microchip t echnology inc. 333 pierce road, suite 180 itasca, il 60143 t el: 630-285-0071 f ax: 630-285-0075 dallas microchip t echnology inc. 14651 dallas p ar kw a y , suite 816 dallas , tx 75240-8809 t el: 972-991-7177 f ax: 972-991-8588 da yton microchip t echnology inc. t w o prestige place , suite 150 miamisb urg, oh 45342 t el: 937-291-1654 f ax: 937-291-9175 los ang eles microchip t echnology inc. 18201 v on kar man, suite 1090 ir vine , ca 92612 t el: 714-263-1888 f ax: 714-263-1338 ne w y ork microchip t echnology inc. 150 motor p ar kw a y , suite 202 hauppauge , ny 11788 t el: 516-273-5305 f ax: 516-273-5335 san jose microchip t echnology inc. 2107 nor th first street, suite 590 san jose , ca 95131 t el: 408-436-7950 f ax: 408-436-7955 t or onto microchip t echnology inc. 5925 air por t road, suite 200 mississauga, ontar io l4v 1w1, canada t el: 905-405-6279 f ax: 905-405-6253 asia/p a cific hong k ong microchip asia p aci c rm 3801b , t o w er t w o metroplaza 223 hing f ong road kw ai f ong, n.t ., hong k ong t el: 852-2-401-1200 f ax: 852-2-401-3431 india microchip t echnology inc. india liaison of ce no . 6, legacy , con v ent road bangalore 560 025, india t el: 91-80-229-0061 f ax: 91-80-229-0062 japan microchip t echnology intl. inc. bene x s-1 6f 3-18-20, shin y ok ohama k ohoku-k u, y ok ohama-shi kanaga w a 222-0033 j apan t el: 81-45-471- 6166 f ax: 81-45-471-6122 k orea microchip t echnology k orea 168-1, y oungbo bldg. 3 floor samsung-dong, kangnam-k u seoul, k orea t el: 82-2-554-7200 f ax: 82-2-558-5934 shanghai microchip t echnology rm 406 shanghai golden br idge bldg. 2077 y an?n road w est, hong qiao distr ict shanghai, prc 200335 t el: 86-21-6275-5700 f ax: 86 21-6275-5060 singapore microchip t echnology singapore pte ltd. 200 middle road #07-02 pr ime centre singapore 188980 t el: 65-334-8870 f ax: 65-334-8850 asia/p a cific (contin ued) t aiwan, r.o .c microchip t echnology t aiw an 10f-1c 207 t ung hua nor th road t aipei, t aiw an, r oc t el: 886-2-2717-7175 f ax: 886-2-2545-0139 eur ope united kingdom ar iz ona microchip t echnology ltd. 505 eskdale road winnersh t r iangle w okingham ber kshire , england rg41 5tu t el: 44-1189-21-5858 f ax: 44-1189-21-5835 france ar iz ona microchip t echnology sarl zone industr ielle de la bonde 2 rue du buisson aux f r aises 91300 massy , f r ance t el: 33-1-69-53-63-20 f ax: 33-1-69-30-90-79 german y ar iz ona microchip t echnology gmbh gusta v-heinemann-ring 125 d-81739 m?chen, ger man y t el: 49-89-627-144 0 f ax: 49-89-627-144-44 ital y ar iz ona microchip t echnology srl centro direzionale colleoni p alazz o t aur us 1 v . le colleoni 1 20041 ag r ate br ianza milan, italy t el: 39-39-6899939 f ax: 39-39-6899883 4/3/98 w orldwide s ales and s ervice microchip receiv ed iso 9001 quality system cer ti cation f or its w or ldwide headquar ters , design, and w af er f abr ication f acilities in j an uar y , 1997. our eld-prog r ammab le picmicro 8-bit mcus , ser ial eepr oms , related specialty memor y products and de v elopment systems conf or m to the str ingent quality standards of the inter national standard organization (iso).

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